参数资料
| 型号： | EVAL-ADE7763ZEB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7763 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7763 |
| 已供物品： | 板 |
| 相关产品： | ADE7763ARSZRLDKR-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLCT-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLTR-ND - IC ENERGY METERING 1PHASE 20SSOP |
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Data Sheet
input. Reading the RSTVPEAK and RSTIPEAK registers clears
their respective contents after the read operation.
INTERRUPTS
Interrupts are managed through the interrupt status register
(STATUS[15:0]) and the interrupt enable register
(IRQEN[15:0]). When an interrupt event occurs, the
corresponding flag in the status register is set to Logic 1—see
the Interrupt Status Register section. If the enable bit for this
interrupt in the interrupt enable register is Logic 1, the IRQ
logic output will go active low. The flag bits in the status register
are set irrespective of the state of the enable bits.
To determine the source of the interrupt, the system master
(MCU) should perform a read from the status register with
reset (RSTSTATUS[15:0]). This is achieved by carrying out a
read from Address 0Ch. The IRQ output goes logic high after
the completion of the interrupt status register read command—
see the Interrupt Timing section. When carrying out a read
with reset, the ADE7763 is designed to ensure that no interrupt
events are missed. If an interrupt event occurs as the status
register is being read, the event will not be lost and the IRQ
logic output will be guaranteed to go high for the duration of
the interrupt status register data transfer before going logic low
again to indicate the pending interrupt. See the next section for
a more detailed description.
ADE7763
Using Interrupts with an MCU
mentation of ADE7763 interrupt management using an MCU.
At time t 1 , the IRQ line goes active low, indicating that one or
more interrupt events have occurred. Tie the IRQ logic output to
a negative edge-triggered external interrupt on the MCU.
Configure the MCU to start executing its interrupt service
routine (ISR) when a negative edge is detected on the IRQ line.
After entering the ISR, disable all interrupts by using the global
interrupt enable bit. At this point, the MCU IRQ external
interrupt flag can be cleared to capture interrupt events that
occur during the current ISR. When the MCU interrupt flag is
cleared, a read f rom the status register with reset is carried out.
This causes the IRQ line to reset to logic high (t 2 )—see the
to determine the source of the interrupt(s) and, therefore, the
appropriate action to be taken. If a subsequent interrupt event
occurs during the ISR, that event will be recorded by the MCU
external interrupt flag being set again (t 3 ). Upon the completion
of the ISR, the global interrupt mask is cleared (same
instruction cycle) and the external interrupt flag causes the
MCU to jump to its ISR again. This ensures that the MCU does
not miss any external interrupts.
t 1
t 2
t 3
MCU
INTERRUPT
FLAG SET
IRQ
MCU
PROGRAM
SEQUENCE
JUMP
TO
ISR
GLOBAL
INTERRUPT
MASK SET
CLEAR MCU
INTERRUPT
FLAG
READ
STATUS WITH
RESET (0x0C)
ISR ACTION
(BASED ON STATUS CONTENTS)
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
JUMP
TO
ISR
Figure 37. Interrupt Management
CS
t 1
SCLK
t 9
DIN
0
0
0
0
0
1
0
1
t 11
t 11
DOUT
DB7
DB0 DB7
DB 0
READ STATUS REGISTER COMMAND
STATUS REGISTER CONTENTS
IRQ
Figure 38. Interrupt Timing
Rev. C | Page 19 of 56
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