参数资料
| 型号： | EVAL-ADE7763ZEB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7763 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7763 |
| 已供物品： | 板 |
| 相关产品： | ADE7763ARSZRLDKR-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLCT-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLTR-ND - IC ENERGY METERING 1PHASE 20SSOP |
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ADE7763
–88.0
–88.5
–89.0
–89.5
–90.0
Data Sheet
frequency noise, necessitating a more effective antialiasing filter
to avoid noise due to aliasing—see the Antialias Filter section.
When the digital integrator is switched off, the ADE7763 can be
used directly with a conventional current sensor such as a current
transformer (CT) or with a low resistance current shunt.
ZERO-CROSSING DETECTION
The ADE7763 has a zero-crossing detection circuit on Channel 2.
This zero crossing is used to produce an external zero-crossing
signal (ZX), which is used in the calibration mode (see the
–90.5
10 2
10 3
initiate a temperature measurement (see the Temperature
Measurement section).
FREQUENCY (Hz)
Figure 29. Combined Phase Response of the
Digital Integrator and Phase Compensator
the output of LPF1.
–1.0
? 1, ? 2, ? 1,
? 8, ? 16
REFERENCE
–1.5
–2.0
V2
V2P
V2N
{GAIN[7:5]}
PGA2
ADC 2
1
–63% TO +63% FS
TO
MULTIPLIER
–2.5
–3.0
–3.5
–4.0
LPF1
f – 3dB = 140Hz
ZERO
CROSSING
ZX
–4.5
–5.0
1.0
0.93
2.32° @ 60Hz
ZX
–5.5
–6.0
40
45
50
55
60
65
70
V2
LPF1
FREQUENCY (Hz)
Figure 30. Combined Gain Response of the
Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
–89.70
–89.75
–89.80
–89.85
–89.90
–89.95
–90.00
–90.05
Figure 32. Zero-Crossing Detection on Channel 2
The ZX signal goes logic high upon a positive-going zero
crossing and logic low upon a negative-going zero crossing on
Channel 2. The ZX signal is generated from the output of LPF1.
LPF1 has a single pole at 140 Hz (@ CLKIN = 3.579545 MHz).
As a result, there is a phase lag between the analog input signal
V2 and the output of LPF1. The phase response of this filter is
shown in the Channel 2 Sampling section. The phase lag response
of LPF1 results in a time delay of approximately 1.14 ms
(@ 60 Hz) between the zero crossing on the analog inputs of
Channel 2 and the rising or falling edge of ZX.
Zero-crossing detection also drives the ZX flag in the interrupt
status register. The ZX flag is set to Logic 1 on the rising and
falling edge of the voltage waveform. It remains high unti l the
–90.10
40
45 50 55 60 65
FREQUENCY (Hz)
Figure 31. Combined Phase Response of the
70
status register is read with reset. An active low in the IRQ
output appears if the corresponding bit in the interrupt enable
register is set to Logic 1.
Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a –20 dB/dec attenuation and
approximately a –90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. The di/dt sensor
has a 20 dB/dec gain. It also generates significant high
The flag in the interrupt status register and the IRQ output are
set to their default values when reset (RSTSTATUS) is read in
the interrupt status register.
Zero-Crossing Timeout
Zero-crossing detection has an associated timeout register,
ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB)
Rev. C | Page 16 of 56
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