参数资料
| 型号： | EVAL-ADE7763ZEB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7763 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7763 |
| 已供物品： | 板 |
| 相关产品： | ADE7763ARSZRLDKR-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLCT-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLTR-ND - IC ENERGY METERING 1PHASE 20SSOP |
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ADE7763
× 1, × 2, × 4,
× 8, × 16
2.42V
REFERENCE
Data Sheet
V2P
{GAIN[7:5]}
V2
V2N
PGA2
ADC 2
LPF1
ACTIVE AND REACTIVE
ENERGY CALCULATION
VRMS CALCULATION
AND WAVEFORM
V1
ANALOG
INPUT RANGE
0.5V, 0.25V, 0.125V,
62.5mV, 31.25mV
0V
0x2852
0x2581
LPF OUTPUT
WORD RANGE
SAMPLING
(PEAK/SAG/ZX)
0x0000
0xDAE8
0xD7AE
Figure 47. ADC and Signal Processing in Channel 2
VOLTAGE SIGNAL (V(t))
0x2518
VRMOS[11:0]
0x0
0xDAE8
sgn 2 9 2 8
2 2 2 1 2 0
VRMS[23:0]
CHANNEL 2
LPF1
|x|
LPF3
+
+
0x17D338
0x00
Figure 48. Channel 2 RMS Signal Processing
Channel 2 has only one analog input range (0.5 V differential).
Like Channel 1, Channel 2 has a PGA with gain selections of 1,
2, 4, 8, and 16. For energy measurement, the output of the ADC
is passed directly to the multiplier and is not filtered. An HPF is
not required to remove any dc offset; it is only required that the
offset is removed from one channel to eliminate errors caused
by offsets in the power calculation. In waveform sampling mode,
one of four output sample rates can be chosen by using Bits 11
and 12 of the mode register. The available output sample rates
are 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode
indicates that a sample is available by going active low. The
Channel 2 RMS Calculation
rms estimation on Channel 2. This Channel 2 rms estimation is
done in the ADE7763 using the mean absolute value calculation,
as shown in Figure 48.The Channel 2 rms value is processed
from the samples used in the Channel 2 waveform sampling
mode. The rms value is slightly attenuated due to LPF1. The
Channel 2 rms value is stored in the unsigned, 24-bit VRMS
register. The update rate of the Channel 2 rms measurement is
CLKIN/4. The Channel 2 rms measurement has a settling time
of approximately 670 ms.
With the specified full-scale ac analog input signal of 0.5 V, the
output from LPF1 swings between 0x2518 and 0xDAE8 at
60 Hz—see the Channel 2 ADC section. The equivalent rms
value of this full-scale ac signal is approximately 1,561,400
(0x17 D338) in the VRMS register. The voltage rms measure-
ment provided in the ADE7763 is accurate to within ±0.5% for
signal input between full scale and full scale/20. The conversion
from the register value to volts must be done externally in the
microprocessor using a volts/LSB constant. Because the low-pass
filter used for calculating the rms value is imperfect, there is some
ripple noise from 2 ω term present in the rms measurement. To
minimize the effect of noise in the reading, synchronize the rms
reading with the zero crossings of the voltage input.
Channel 2 RMS Offset Compensation
The ADE7763 incorporates a Channel 2 rms offset
compensation register (VRMSOS). This is a 12-bit, signed
register that can be used to remove offset in the Channel 2 rms
calculation. An offset could exist in the rms calculation due to
input noises and dc offset in the input samples. One LSB of the
Channel 2 rms offset is equivalent to 1 LSB of the rms register.
Assuming that the maximum value of the Channel 2 rms
calculation is 1,561,400d with full-scale ac inputs, then 1 LSB of
the Channel 2 rms offset represents 0.064% of measurement
error at –60 dB down of full scale.
VRMS = VRMS 0 + VRMSOS (6)
where VRMS 0 is the rms measurement without offset
correction.
The voltage rms offset compensation should be done by testing
the rms results at two nonzero input levels. One measurement
can be done close to full scale and the other at approximately
full scale/10. The voltage offset compensation can be derived
from these measurements. If the voltage rms offset register does
not have enough range, the CH2OS register can also be used.
PHASE COMPENSATION
When the HPF is disabled, the phase error between Channel 1
and Channel 2 is 0 from dc to 3.5 kHz. When HPF is enabled,
Channel 1 has the phase response illustrated in Figure 50 and
Rev. C | Page 24 of 56
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