参数资料
| 型号： | EVAL-ADE7763ZEB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 34/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7763 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7763 |
| 已供物品： | 板 |
| 相关产品： | ADE7763ARSZRLDKR-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLCT-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLTR-ND - IC ENERGY METERING 1PHASE 20SSOP |
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Time =
× 1 . 2 μ s = 888 s = 12 . 52 min (28)
ADE7763
Integration Times under Steady Load
As mentioned in the last section, the discrete time sample
period ( T ) for the accumulation register is 1.1 μs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 0x000, the average word value from the
apparent power stage is 0xA D055. The maximum value that
can be stored in the apparent energy register before it overflows
is 2 24 or 0xFF FFFF. The average word value is added to the
internal register, which can store 2 48 or 0xFFFF FFFF FFFF
before it overflows. Therefore, the integration time under these
conditions with VADIV = 0 is calculated as follows:
0xFFFF FFFF FFFF
0xAD055
When VADIV is set to a value other than 0, the integration time
varies, as shown in Equation 29.
Time = Time WDIV = 0 × VADIV (29)
LINE APPARENT ENERGY ACCUMULATION
The ADE7763 is designed with a special apparent energy
accumulation mode, which simplifies the calibration process.
Data Sheet
By using the on-chip zero-crossing detection, the ADE7763
accumulates the apparent power signal in the LVAENERGY
register for an integral number of half cycles, as shown in
always active.
The number of half line cycles is specified in the LINECYC
register, which is an unsigned, 16-bit register. The ADE7763 can
accumulate apparent power for up to 65,535 combined half
cycles. Because the apparent power is integrated on the same
integral number of line cycles as the line active energy register,
these two values can be easily compared. The active and apparent
energies are calculated more accurately because of this precise
timing control. At the end of an energy calibration cycle, the
CYCEND flag in the interrupt status register is set. If the
CYCEND mask bit in the interrupt mask register is enabled, the
IRQ output also will go active low. Thus, the IRQ line can also
be used to signal the end of a calibration.
The line apparent energy accumulation uses the same signal path
as the apparent energy accumulation. The LSB size of these two
registers is equivalent.
APPARENT
POWER
%
+
+
48
0
LVAENERGY REGISTER IS
VADIV[7:0]
UPDATED EVERY LINECYC
ZERO CROSSINGS WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
LPF1
23
0
FROM
CHANNEL 2
ADC
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
LVAENERGY[23:0]
LINECYC[15:0]
Figure 68. Apparent Energy Calibration
Rev. C | Page 34 of 56
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