参数资料
| 型号： | EVAL-ADE7763ZEB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7763 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7763 |
| 已供物品： | 板 |
| 相关产品： | ADE7763ARSZRLDKR-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLCT-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLTR-ND - IC ENERGY METERING 1PHASE 20SSOP |
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ADE7763
THEORY OF OPERATION
ANALOG INPUTS
Data Sheet
Table 5. Maximum Input Signal Levels for Channel 1
The ADE7763 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
Max Signal
Channel 1
0.5 V
ADC Input Range Selection
0.25 V 0.125 V
and V2P/V2N is ±0.5 V. In addition, the maximum signal level
on analog inputs for V1P/V1N and V2P/V2N is ±0.5 V with
respect to AGND.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the gain register—see
0.5 V
0.25 V
0.125 V
0.0625 V
0.0313 V
0.0156 V
0.00781 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
?
?
?
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
?
?
?
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
the gain selection for the PGA in Channel 2 is made via Bits 5
to 7. Figure 23 shows how a gain selection for Channel 1 is
made using the gain register.
GAIN REGISTER*
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
7 6 5 4 3 2 1 0
7
6
5
GAIN[7:0]
4 3
2
1
0
0
0
0
0
0
0
0
0
ADDR:
0x0F
0
0
0
0
0
0
0
0
PGA 2 GAIN SELECT
000 = × 1
PGA 1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
001 = × 2
010 = × 4
V1P
GAIN (K)
SELECTION
011 = × 8
100 = × 16
* REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
011 = × 8
100 = × 16
CHANNEL 1 FULL-SCALE SELECT
00 = 0.5V
01 = 0.25V
10 = 0.125V
V IN
V1N
K × V IN
+
OFFSET ADJUST
Figure 24. Analog Gain Register
It is also possible to adjust offset errors on Channel 1 and
Channel 2 by writing to the offset correction registers (CH1OS
and CH2OS, respectively). These registers allow channel offsets
in the range ±20 mV to ±50 mV (depending on the gain setting)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
(±50mV)
to be removed. Note that it is not necessary to perform an offset
correction in an energy measurement application if HPF in
CH1OS[7:0]
BITS 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION
BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT OFF)
Figure 23. PGA in Channel 1
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the gain register—see Figure 24. As
previously mentioned, the maximum differential input voltage
is 0.5 V. However, by using Bits 3 and 4 in the gain register, the
maximum ADC input voltage can be set to 0.5 V, 0.25 V, or
0.125 V. This is achieved by adjusting the ADC reference—see
the Reference Circuit section. Table 5 summarizes the
Channel 1 is switched on. Figure 25 shows the effect of offsets
on the real power calculation. As seen from Figure 25, an offset
on Channel 1 and Channel 2 contributes a dc component after
multiplication. Because this dc component is extracted by LPF2
to generate the active (real) power information, the offsets
contribute an error to the active power calculation. This problem
is easily avoided by enabling HPF in Channel 1. By removing
the offset from at least one channel, no error component is
generated at dc by the multiplication. Error terms at cos( ω t) are
removed by LPF2 and by integration of the active power signal
in the active energy register (AENERGY[23:0])—see the Energy
Calculation section.
maximum differential input signal level on Channel 1 for the
various ADC range and gain selections.
Rev. C | Page 14 of 56
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