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| 型号： | FDS8978 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/11页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH DUAL 30V 8-SOIC |
| 产品变化通告： | Mold Compound Change 12/Dec/2007 |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | 2 个 N 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 30V |
| 电流 - 连续漏极(Id) @ 25° C： | 7.5A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 18 毫欧 @ 7.5A，10V |
| Id 时的 Vgs(th)（最大）： | 2.5V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 26nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 907pF @ 15V |
| 功率 - 最大： | 1.6W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 标准包装 |
| 其它名称： | FDS8978DKR |
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B VDSS
Drain to Source Breakdown Voltage
I D = 250 μ A, V GS = 0V
30
-
-
V
I DSS
I GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V DS = 24V
V GS = 0V
V GS = ±20V
T J = 150 o C
-
-
-
-
-
-
1
250
±100
μ A
nA
On Characteristics
V GS(TH)
Gate to Source Threshold Voltage
V GS = V DS , I D = 250 μ A
1.2
-
2.5
V
I D = 7.5A, V GS = 10V
-
14
18
r DS(on)
Drain to Source On Resistance
I D = 6.9A, V GS = 4.5V
I D = 7.5A, V GS = 10V,
T J = 150 o C
-
-
17
22
21
29
m ?
Dynamic Characteristics
C ISS
C OSS
C RSS
R G
Q g(TOT)
Q g(5)
Q gs
Q gs2
Q gd
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Total Gate Charge at 10V
Total Gate Charge at 5V
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V DS = 15V, V GS = 0V,
f = 1MHz
V GS = 0.5V, f = 1MHz
V GS = 0V to 10V V DD = 15V
V GS = 0V to 5V I D = 7.5A
-
-
-
-
-
-
-
-
-
907
191
112
1.2
17
9
2.3
1.5
3.3
1270
-
-
4.0
26
14
-
-
-
pF
pF
pF
?
nC
nC
nC
nC
nC
Switching Characteristics (V GS = 10V)
t ON
t d(ON)
Turn-On Time
Turn-On Delay Time
-
-
44
7
66
10.5
ns
ns
t r
t d(OFF)
t f
t OFF
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
V DD = 15V, I D = 7.5A
V GS = 10V, R GS = 16 ?
-
-
-
-
37
48
24
72
55.5
72
36
108
ns
ns
ns
ns
Drain-Source Diode Characteristics
V SD
t rr
Q RR
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
I SD = 7.5A
I SD = 2.1A
I SD = 7.5A, dI SD /dt = 100A/ μ s
I SD = 7.5A, dI SD /dt = 100A/ μ s
-
-
-
-
-
-
19
10
1.25
1.0
25
13
V
V
ns
nC
Notes:
1: Starting T J = 25°C, L = 1mH, I AS = 7.5A, V DD = 30V, V GS = 10V.
2: R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R θ JC is guaranteed by design while R θ JA is determined by the user’s board design.
a) 78°C/W when mounted on a 0.5 in 2 pad of 2 oz copper.
b) 125°C/W when mounted on a 0.02 in 2 pad of 2 oz copper.
c) 135°C/W when mounted on a minimun pad.
?2011 Fairchild Semiconductor Corporation
FDS8978 Rev. B1
2
www.fairchildsemi.com
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