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参数资料
| 型号： | GP2021 |
| 厂商： | Mitel Networks Corporation |
| 英文描述： | GPS 12 channel Correlator Advance Information |
| 中文描述： | 全球定位系统12通道相关器研究进展信息 |
| 文件页数： | 29/62页 |
| 文件大小： | 372K |
| 代理商： | GP2021 |
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35
GP2021
Table 13: TIC period setting
FRONT_END_MODE
Preset Loaded
TIC Period
(In SYSTEM_SETUP)
Low (Real_Input mode)
0x08B823
(2885+1)* (7/40MHz) = 505.0500
s
High (Complex_Input mode)
0x08E6A4
(4985+1)* (6/35MHz) = 854.74286
s
RESET_CONTROL
(Write Address)
Bit
Bit Name
15
Not used.
14
Not used.
13
Not used.
12
CH11_RSTB
11
CH10_RSTB
10
CH9_RSTB
9 CH8_RSTB
8 CH7_RSTB
7 CH6_RSTB
6 CH5_RSTB
5 CH4_RSTB
4 CH3_RSTB
3 CH2_RSTB
2 CH1_RSTB
1 CH0_RSTB
0 MRB, Active LOW software
master reset
MRB: When Low (a software reset), the effect is similar to
a hardware reset except that the clock generator, the time
base generators, measurement data and peripheral functions
are not affected and the Status bits ACCUM_INT, DISCIP,
DISCIP_GLITCH, MEAS_INT, and TIC are not reset. MRB
should be set to High to allow access to all of the various
registers. MRB is set High by a hardware reset.
CHx_RSTB: When set active Low, the reset bit inhibits
propagation of the clock phases to the CHx tracking channel
and resets the Accumulated Data flags, Code DCO and
Carrier DCO accumulators, the I & D accumulators, and the
Code Phase Counter. A CHx_RSTB does not reset the Carrier
Cycle, Code Slew or the Epoch counters. At the end of the
reset, the channel enable resets the code generator to a
previously programmed start phase. This is all required for the
parallel search algorithm of one satellite signal using many
channels in order to start from a known relative code phase on
all the channels. All of the control registers in CHx can be
programmed and read as usual during the reset state. To
restart normal operation in several different channels at the
same time, the corresponding CHx_RSTB bits should be set
to High during the same write operation. All CHx_RSTB are
set Low by a master reset, (both hardware and software), so
a write Low to bit 0 of this register will force a Low onto bits 12
to 1 irrespective of what was on the bus.
Power consumption can be kept to a minimum by setting
CHx_RSTB Low when a channel is not required.
STATUS
(Write Address)
Bits 15 to 0: not used
A write operation to this location, irrespective of the data on the
bus, latches the state of all status bits contained in
ACCUM_STATUS_A,
ACCUM_STATUS_B,
and
ACCUM_STATUS_C registers. Performing a write to
STATUS prior to reading the status registers ensures reading
of stable status values. The latch takes effect within 300 ns of
the trailing edge of the write pulse. The active edge transition
of the ACCUM_INT signal will also latch the state of the status
bits, thus it is not necessary to write to STATUS when the
status registers are to be read as a response to the
ACCUM_INT signal in an interrupt handling routine. The write
to STATUS is required only when the status registers are read
at times that are not synchronised to the interrupts. These two
mechanisms are mutually exclusive and should not be used
together – if both are used, a write to STATUS soon after the
occurrence of an ACCUM_INT signal can result in confused
readings. To avoid conflict the INTERRUPT_ENABLE in the
SYSTEM_SETUP register should be set to Low if writes to
STATUS are to be used.
If the INTERRUPT_ENABLE bit in SYSTEM_SETUP
register is set to Low, the interrupt will not latch the status bits
in the status registers, but a STATUS write access will do so.
SYSTEM_SETUP
(Write Address)
Bit
Bit Name
15 to 11 Not used
10
MEAS_INT_SOURCE
9 OPS_DRIVE_SEL
8 IPS_3V_MODE
7 INTERRUPT_PERIOD
6 FRONT_END_MODE
5 INTERRUPT_ENABLE
4 DISCOP_SELECT_100KHZ
3 DISCOP_SELECT_TIMEMARK
2 DISCOP_SELECT_CH0_DUMP
1 DISCOP
0 CARRIER_MIX_DISABLE
MEAS_INT_SOURCE: When set High the MEAS_INT
output is cleared by a read of MEAS_STATUS_A, when Low
by a read of ACCUM_STATUS_B. A master reset forces the
MEAS_INT_SOURCE bit Low.
OPS_DRIVE_SEL: When set High this control bit
increases the size of the output driver on ACCUM_INT,
MEAS_INT, and D(15:0) pins so as to increase the drive of
these pins if they are driving a large load. Master reset forces
OPS_DRIVE_SEL to Low.
IPS_3V_MODE: When set High this control bit sets the
input buffers on SIGN0, MAG0, SIGN1, and MAG1 for signals
centred on mid–supply, for use with a Front–end running from
a 3V supply. When Low, sets the thresholds to TTL levels, for
5V operation. Master reset forces IPS_3V to Low.
INTERRUPT_PERIOD: When Low, the approximate
interrupt period is set to 505 s and when High it is set to 854
s.
For
more
detail
see
the
description
of
PROG_ACCUM_INT.
Master
reset
forces
INTERRUPT_PERIOD bit to Low.
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