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参数资料
| 型号： | GP2021 |
| 厂商： | Mitel Networks Corporation |
| 英文描述： | GPS 12 channel Correlator Advance Information |
| 中文描述： | 全球定位系统12通道相关器研究进展信息 |
| 文件页数： | 35/62页 |
| 文件大小： | 372K |
| 代理商： | GP2021 |
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40
GP2021
DATA_RETENT
(Write / Read Address)
This is a byte wide Read/Write register which can be used
to store a predetermined value, which can be interrogated in
order to determine whether a total power loss (below the data
retention level ) has occurred.
General Control
IO_CONFIG
(Write / Read Address)
The IO_CONFIG register is a full 16 bit wide read/write
register containing two separate elements: A 16 bit wide read
location which allows the controlling microprocessor to view
the input level on all the Discrete and Multi Function inputs,
and a 16 bit wide write location for configuration of the
Discreteand Multi Function I/O pins.
IO_CONFIG Read: A read of the IO_CONFIG address
will latch the logic level of a number of input pins and output
these levels to the microprocessor via the 16 bit data bus. This
allows the microprocessor to read the input levels on all the
Discrete and Multi Function Inputs from a single location. The
bit allocations are as follows:
Bit
Input Pin
15
RXB
14
RXA
13
DISCOP
12
DISCIP
11
MAG1
10
SIGN1
9
MAG0
8
SIGN0
7
MULTI_FN_IO
6
NBRAM
5
DISCIO
4
NARMSYS
3
NBW/WRPROG
2
NMREQ
1
NOPC/NINTELMOT
0
NRW
It should be noted that the usefulness of a number of these
inputs as Discrete Inputs for System Control is dependant
upon the Interface Mode of the GP2021. For instance it is
possible to use the NOPC/NINTELMOT pin as a Discrete
Input in ARM System mode if the DEBUG function is disabled,
whereas this pin could not be used as a Discrete Input in
Standard Interface Mode. Similarly, NMREQ could be used
as a Discrete Input in Standard Interface Mode but not in ARM
System Mode.
IO_CONFIG Write: The IO_CONFIG write location
allows the configuration of the multi purpose I/O pins DISCIO
and MULTI_FN_IO. The register bit assignments are as
follows:
Bit
Bit Name
15 to 13
Not Used
12
MULTI_FN_IO_SELECT_TIMEMARK
11
MULTI_FN_IO_SELECT_100KHZ
10
MULTI_FN_IO_LEVEL
9 to 8
MULTI_FN_IO_CONFIG
7 to 4
Not Used
3
DISCIO_SELECT_TIMEMARK
2
DISCIO_SELECT_100KHZ
1
DISCIO_LEVEL
0
DISCIO_CONFIG
DISCIO_CONFIG: When set High this bit configures the
DISCIO pin as a Discrete Output, when low the DISCIO pin is
configured as a Discrete Input. A Master Reset sets the
DISCIO_CONFIG bit Low.
DISCIO_SELECT TIMEMARK,
DISCIO_SELECT_100KHZ,
DISCIO_LEVEL:
When configured as an output, the DISCIO pin can be
setup to give a signal as determined by Table 20.
At power on reset, the DISCIO output value = 0 setting is
chosen. The 100kHz square wave is derived from the Master
Clock and is useful for measuring its drift.
MULTI_FN_IO_SELECT TIMEMARK,
MULTI_FN_IO_SELECT_100KHz,
MULTI_FN_IO_LEVEL:
When configured as an output, the MULTI_FN_IO pin
can be setup to give a signal as shown in Table 21
Bit
DISCIO output value
32
1
00
0
00
1
0
1
X
100kHz square wave
0
X
TIMEMARK
Table 20: DISCIO output selection.
Bit
DISCIO output value
12
11
10
00
0
00
1
0
1
X
100kHz square wave
0
X
TIMEMARK
Table 21: MULTI_FN_IO output selection.
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