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参数资料
| 型号： | GP2021 |
| 厂商： | Mitel Networks Corporation |
| 英文描述： | GPS 12 channel Correlator Advance Information |
| 中文描述： | 全球定位系统12通道相关器研究进展信息 |
| 文件页数： | 62/62页 |
| 文件大小： | 372K |
| 代理商： | GP2021 |
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9
GP2021
cases TIMEMARK rising edges are generated co–incident
with the rising edges of TIC. Therefore, for TIMEMARK to be
aligned with UTC, TIC must be aligned with UTC. This is done
by modifying the TIC period for a single TIC cycle, then setting
it back to its original value, thus slewing the phase of TIC.
TIMEMARK
may
be
generated
by
setting
the
TIMEMARK_ARM bit in the TIMEMARK_CONTROL register,
in which case the next TIC will generate a rising edge at
TIMEMARK and clear the TIMEMARK_ARM bit. Alternatively
TIMEMARK may be generated as a programmable integer
number of TIC’s, again under the control of the
TIMEMARK_CONTROL register.
Status Registers
There are four status registers (ACCUM_STATUS_A, _B,
_C and MEAS_STATUS_A). These contain flags associated
with the accumulated and measurement data held on each of
the 12 channels. Some system level status bits also appear in
these registers.
Sample Latches
The Sample Latches synchronise data from the front end
to the internal SAMPCLK. In Real_Input mode the down
converted satellite signal can be sampled at the output of the
front end by SAMPCLK. This data is then input to the GP2021
as 2 bit data on either the SIGN0, MAG0, or SIGN1, MAG1
inputs, where it is re–sampled at the next rising edge of
SAMPCLK. These signals are then distributed to the 12
tracking modules.
When a GP2015 or GP2010 front end is used, the data
represents a band–limited signal at an IF centered on
4.309MHz. Sampling at 5.714MHz aliases it to an IF of
1.405MHz.
In Complex_Input mode, the down converted satellite
signal is applied direct to the GP2021 at its SIGN0, MAG0,
SIGN1, MAG1 inputs, which act as In–Phase Sign, In–Phase
Magnitude, Quadrature Sign and Quadrature Magnitude
respectively. These signals are sampled at 5.833MHz within
the correlator and then passed to the tracking modules.
Address Decoder
The Address Decoder performs address decoding for the
correlator.
Bus Interface
The Bus Interface controls the transfer of data between the
external 16 bit wide data bus and the internal 32 bit data bus.
Apart from the code and carrier DCO increment values, all
data transfers are 16 bits wide. Write operations to the code
and carrier DCO’s are 32 bit data transfers, in which the High
16 bit word must be written immediately before the low 16 bit
word. Note that the write cycle to write cycle delay of 300 ns
referred to in the Microprocessor Interface does not apply
between the first and second write cycles for 32 bit DCO data
transfers. For further information see the Microprocessor
Interface section.
TRACKING MODULES
The Tracking Modules are 12 identical signal tracking
channels numbered CH0 to CH11, each with the block
diagram shown in Fig 5. These blocks generate the data used
to track the satellite signals. There is no overwrite protection
mechanism on this data. For further information see the
section on CONTROLLING THE GP2021.
Each Tracking Channel can be individually programmed to
operate in either Update or Preset mode. Update mode is the
normal mode of operation. Preset mode is a special mode of
operation where writes to certain registers are delayed until
the next TIC to allow synchronisation of registers and
presetting of the code DCO phase. For further information see
the Preset Mode section in the Detailed Operation of the
GP2021.
The individual sub–blocks in the tracking modules are:
Carrier DCO
The Carrier DCO, which is clocked at the SAMPCLK
frequency, is used to synthesise the digital local oscillator
signal required to bring the input signal to baseband in the
mixer block, and must be adjusted away from its nominal value
to allow for Doppler shift and reference frequency error.
When used with the GP2015/GP2010 the nominal
frequency of this signal is 1405396825 MHz (with a resolution
of 42.57475 MHz) and is set by loading the 26 bit register
CHx_CARRIER_DCO_INCR. This very fine resolution is
needed so that the DCO will stay in phase with the satellite
signal for an adequate time. The Carrier DCO Phase cannot
be directly set, but must be adjusted by altering the frequency.
The Carrier DCO outputs are 4 level, 8 phase sinusoidals
with the following sequences over one cycle:
As the clock to the DCO is normally less than 8 times the
output frequency, not all phases are generated in every cycle.
With a typical clock frequency of 5714 MHz and an output
frequency of 1405 MHz there are only around 4 phases per
cycle. These will slide through the cycle as time progresses to
cover all values.
Code DCO
The Code DCO is similar to the Carrier DCO block. It is also
clocked at the SAMPCLK frequency and synthesises the
oscillator required to drive the code generator at twice the
required chipping rate. The nominal frequency of the output is
2046 MHz, to give a chip rate of 1023 MHz and is set by
loading the 25 bit register CHx_CODE_DCO_INCR.
It is programmed with a resolution of 8514949 mHz when
used with a GP2015/GP2010 front end. The very fine
resolution is again needed to keep the DCO in phase with the
satellite signal. The Code DCO Phase can only be set to the
exact satellite phase in Preset mode. In Update mode, it must
be aligned with the satellite phase by adjusting its frequency.
Carrier Cycle Counter
The Carrier Cycle Counter is 20 bits long, and keeps a
count of the number of cycles of the Carrier DCO between
TIC’s. This is not needed for a basic navigation system but
may be used to measure the range change (delta–range) to
each satellite between TIC’s. The delta ranges can be used to
smooth the code pseudo–ranges. For finer detail the Carrier
DCO phase may also be read at each TIC to give the fractional
part of the cycle count or delta–range.
C/A Code Generator
The C/A Code Generator generates the selected Gold
code for a GPS satellite (1 to 32), a ground transmitter
(pseudolite, 33 to 37), an INMARSAT–GIC satellite (201 to
211) or a GLONASS satellite. A Gold code is selected by
writing a specific pattern of 10 bits, as listed in the section
‘Detailed Description of Registers’, to the CHx_SATCNTL
register, or by setting the GPS_NGLON bit to Low for the
GLONASS code. Two outputs are generated to give both a
PROMPT and a TRACKING signal. The TRACKING signal
can be set to one of four modes: EARLY (one half chip before
the PROMPT signal), LATE (one half chip behind),
DITHERED (toggled between EARLY and LATE every 20ms)
or EARLY–MINUS–LATE (the signed difference).
The output code is a sequence of +1’s and –1’s for all code
types except EARLY–MINUS–LATE where the result can also
Destination Arm
I
LO
Q
LO
Sequence
–1+1+2+2+1–1–2–2
+2+2+1–1–2–2–1+1
Table 1 Carrier DCO outputs
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