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参数资料
| 型号： | GP2021 |
| 厂商： | Mitel Networks Corporation |
| 英文描述： | GPS 12 channel Correlator Advance Information |
| 中文描述： | 全球定位系统12通道相关器研究进展信息 |
| 文件页数： | 38/62页 |
| 文件大小： | 372K |
| 代理商： | GP2021 |
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43
GP2021
ELECTRICAL CHARACTERISTICS(cont.)
T amb = –40
°C to 85 °C, V DD = 5V 10%. The input thresholds and output voltage limits for the logic signal pins are
tested and guaranteed by production test. All other parameters are guaranteed by characterisation and design. They apply
within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Value
Characteristics
Symbol
Min
Typ
Max
Units
Conditions
Power level 6 Outputs: types OP6
and OPT6
Output Voltage High
V
OH
0.8V
DD
VI
OH = –12mA
Output Voltage Low
V OL
0.4
V
I
OL = 12mA
Output short
IOS
270
mA
V
DD = max VO = V DD
circuit current
150
mA
V
DD = max VO = 0V
Tri–state output leakage current
IOZ
<10
A
VOH = GND or V DD
Output capacitance
COUT
5
pF
Power Level 3 Outputs : types OP3
and OPT3
Output Voltage High
V
OH
0.8V
DD
VI
OH = –6mA
Output voltage Low
V
OL
0.4
V
I
OL = 6mA
Output short
IOS
135
mA
V
DD = max VO = V DD
circuit current
75
mA
V
DD = max VO = 0V
Tri–state output leakage current
IOZ
<10
A
VOH = GND or V
DD
Output capacitance
COUT
5
pF
Power Level 2 Outputs: types OP2
and OPT2
Output voltage High
V
OH
0.8V
DD
VI
OH = –4mA
Output voltage Low
V
OL
0.4
V
I
OL = 4mA
Output short
IOS
90
mA
V
DD = max VO = VDD
circuit current
50
mA
V
DD = max VO =0V
Tri–state output leakage current
IOZ
<10
A
VOH = GND or V
DD
Output capacitance
COUT
5
pF
Power Level 1 Outputs: types OP1
and OPT1
Output Voltage High
V
OH
0.8V DD
V
I
OH = –2mA
Output Voltage Low
V
OL
0.4
V
I
OL = 2mA
Output short
IOS
45
mA
V
DD = max VO = VDD
circuit current
25
mA
V
DD = mx VO = VDD
Tri–state output leakage current
IOZ
<10
A
VOH = GND or V
DD
Output capacitance
COUT
5
pF
Note 1: Any unused inputs must be tied High or Low.
Note 2: The input pair CLK_T, CLK_I may be driven by CMOS logic levels (D.C. coupled) or A.C. coupled or by a low amplitude differential
sinewave (D.C. coupled e.g. GP2010). If a single logic level is to be used this should drive CLK_T with the CLK_I pin biased to mid supply.
If a single sinewave clock is to be used this should drive CLK_T through a capacitor, with both of the CLK_T/CLK_I pins biased to
approximately two thirds supply. See Fig. 24 for a suggested circuit.
Note 3: These values apply when the 32kHz oscillator circuit is not running.
Note 4: The operation of the feature whereby input levels and output drive strengths can be modified is not guaranteed by the existing factory
testing procedure.
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