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参数资料
| 型号： | GP2021 |
| 厂商： | Mitel Networks Corporation |
| 英文描述： | GPS 12 channel Correlator Advance Information |
| 中文描述： | 全球定位系统12通道相关器研究进展信息 |
| 文件页数： | 56/62页 |
| 文件大小： | 372K |
| 代理商： | GP2021 |
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6
GP2021
Pin No
Signal Name
Type
Description ARM System Mode
Description Standard Interface
Mode
31
ABORT/ MICRO_CLK
O
Abort output to the microprocessor.
20MHz Clock output. Provides a
Generates a valid ARM Data Abort
20MHz clock with a 1:1
sequence, triggered by a rising edge
mark-to-space ratio
at MULTI_FN_IO if this function is
enabled.
32
DISCIO
I/O
Multi–purpose discrete input / output. After a GP2021 reset it is
configured as an input.
33
A22 / READ
I
Address input from the microprocessor.
Read input from the
A<22:20> are decoded to select the
microprocessor. In Intel mode
address space partitioning.
it is the active Low read strobe.
In Motorola mode it is the Read
(High)/Write (Low) select line.
36
A21 / NCS
I
Address input from the microprocessor.
GP2021 Chip Select input
A<22:20> are decoded to select the
(Active Low).
address space partitioning.
37
A20 / WREN
I
Address input from the microprocessor
Write–Read Strobe input from
A<22:20> are decoded to select the
the microprocessor. In Intel
address space partitioning.
mode it is the active Low write
strobe. In Motorola mode it is
the active High Write-Read
strobe.
38 – 45
A<9:2>
I
Address Inputs <9:2> from the microprocessor. These allow register
selection.
46
A1 / ALE_IP
I
Address input 1 from the
Address Latch Enable input
microprocessor. A<1:0> are decoded
from microprocessor (Active
to provide individual byte write
High)
selection via NW<3:0>.
47
A0 / NRESET_IP
I
Address input 0 from the
Reset input (Active Low).
microprocessor. A<1:0> are decoded
to provide individual byte write
selection via NW<3:0>.
48– 54,
D<0:15>
I/O
Bidirectional data bus.
57–65
66
PLL_LOCK
I
PLL Lock Indicator input from RF section. When High this signa
indicates that the PLL within the RF section is in lock and the master
clock inputs have stabilised.
68
DISCOP
O
Multi–purpose discrete output.
70
CLK_T
I
Master clock input (40MHz).
71
CLK_I
I
Inverted Master clock input.
73
SAMPCLK
O
Sample Clock output to the front end. Provides a 5.714MHz clock with a
4:3 mark–to–space ratio.
75
NBRAM / DISCIP4
I
Battery Backed RAM select input.
Multi–purpose discrete input.
Defines the state of the NRAM output in
Power Down mode.
76
SIGN0
I
SIGN0 input from the RF section.
77
MAG0
I
MAG0 input from the RF section.
78
SIGN1
I
SIGN1 input from a second, optional, RF section.
79
MAG1
I
MAG1 input from a second, optional, RF section.
80
DISCIP1
I
Multi–purpose discrete input.
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