参数资料
型号: HI7188IN
厂商: Intersil
文件页数: 1/24页
文件大小: 0K
描述: CONV A/D 16BIT 8:1 MUX 44-MQFP
标准包装: 96
位数: 16
采样率(每秒): 240
数据接口: QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 50mW
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 44-QFP
供应商设备封装: 44-MQFP(10x10)
包装: 管件
输入数目和类型: 8 个差分,单极;8 个差分,双极
1
TM
File Number
4016.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Intersil and Design is a trademark of Intersil Corporation. | Copyright Intersil Corporation 2000
HI7188
8-Channel, 16-Bit, High Precision, Sigma-
Delta A/D Sub-System
The HI7188 is an easy-to-use 8-Channel sigma-delta
programmable A/D subsystem ideal for low frequency
physical and electrical measurements in scientic, medical,
and industrial applications. The subsystem has complete on-
chip capabilities to support moving the intelligence from the
system controller and towards the sensors. This gives the
designer faster and more exible congurability without the
traditional drawbacks of low throughput per channel, higher
power or cost per channel. Extreme design complexity and
excessive software overhead is eliminated.
The HI7188 contains a fully differential 8 channel multiplexer,
Programmable Gain Instrumentation Amplier (PGIA), 4th
order sigma-delta ADC, integrating lter, line noise rejection
lters, calibration and data RAMs, clock oscillator, and a
microsequencer. Communication with the HI7188 is
performed via the serial I/O port, and is compatible with most
synchronous transfer formats, including both the
Motorola/Intersil 6805/11 series SPI, QSPI and Intel 8051
series SSR protocols.
The powerful on-board microsequencer provides automatic
conversions on the multiplexed input channels (up to 8) by
controlling all channel switching, ltering and calibration. The
microsequencer supports on-the-y multiplexer
reconguration, forty to fty times faster throughput than the
competition and zero step response delay during internal or
external multiplexer channel changes. A simple set of
commands gives the user control over calibration, PGIA
gain, and bipolar/unipolar modes on a per channel basis.
Number of channels to convert, data coding, line noise
rejection, etc. is programmed at the chip level. The
calibration RAMs allow the user to read and write system
calibration data while the data RAMs provide a read support
of the conversion results for each channel.
This design is effectively eight 16-bit (for 96dB noise-free
dynamic range) Sigma-Delta A/D converters combined with
a microsequencer and an eight-channel multiplexer in a
single package. The HI7188 provides 120dB line-noise
rejection at 240 samples/second/channel (in 60Hz line-
rejection mode) and 200 samples/second/channel (in 50Hz
line-rejection mode) base output data rates. By reusing
multiplexer channels for the same input, throughput can
Fully Differential 8-Channel Multiplexer and Reference
Features
Fully Differential 8-Channel Multiplexer and Reference
Automatic Channel Switching with Zero Latency
240 Conversions Per Second Per Channel
16-Bit Resolution with No Missing Codes
0.0015% Integral Non-Linearity
Fully Software Congurable
- 120dB Rejection of 60/50Hz Line Noise
- Channel Conversion Order and Number of Active
Channels
- True Bipolar or Unipolar Input Range Per Channel
- PGIA Gain Per Channel
- 2-Wire or 3-Wire Interface
Chopper Stabilized PGIA with Gains of 1 to 8
Serial Data I/O Interface, SPI Compatible
3 Point System Calibration
Low Power Dissipation of 30mW (Typ)
Applications
Multi-Channel Industrial Process Controls
Weight Scales
Medical Patient Monitoring
Laboratory Instrumentation
Gas Monitoring System
Reference Literature
- AN9504 “A Brief Introduction to Sigma Delta
Conversion”
- TB329 “Intersil Sigma-Delta Calibration Techniques”
- AN9518 “Using the HI7188 Evaluation Kit”
- AN9610 “Interfacing the HI7188 to a Microcontroller”
- AN9538 “Using the HI7188 Serial Interface
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
HI7188IN
-40 to 85
44 Ld MQFP
Q44.10x10
HI7188EVAL
25
Evaluation Kit
Data Sheet
December 2000
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