参数资料
型号: IP-SLITE2
厂商: Altera
文件页数: 103/110页
文件大小: 0K
描述: IP SERIALLITE II
标准包装: 1
系列: *
类型: MegaCore
功能: SerialLite II 协议
许可证: 初始许可证
Chapter 5: Testbench
Example Testbench – Verilog HDL
Table 5–12 shows and explains a demonstration testbench main section example,
allowing you to easily modify the testbench. You can change the packet size, port
address, number of packets, and so on, or force certain behavior.
5–17
1
This example testbench may not match your testbench exactly.
Table 5–12. Example of a Demonstration Testbench (Part 1 of 5)
Main Section
//SERIALLITE2_TB_MAIN_START
Comments
Start of the testbench main section; the only section
intended to be modified.
integer pkt_cnt_dat_dut;
integer pkt_cnt_pri_dut;
integer pkt_cnt_dat_sis;
integer pkt_cnt_pri_sis;
//----------------------------------------------
-----------
//Define the number of packets / streaming bytes
to be sent
//----------------------------------------------
-----------
integer packets_to_send; initial packets_to_send
= 5;
integer streaming_bytes; initial streaming_bytes
= 1500;
//----------------------------------------------
-----------
initial begin
#1;
exp_tc_cnt = 1;
err_limit = 0;
tc_start(`TBID);
wait (reset_n == 1);
// initialize packet counters
pkt_cnt_dat_dut = packets_to_send;
pkt_cnt_pri_dut = packets_to_send;
pkt_cnt_dat_sis = packets_to_send;
pkt_cnt_pri_sis = packets_to_send;
wait (linked_up == 1);
Declare packet counters.
Defines the number of packets (5) or streaming bytes
(1,500) to be sent.
Main initial block.
Sets expectation for the number of test cases (checks);
this number must match the number of tc_ s ta r t/tc_e n d
pairs in the testbench, otherwise the testbench is declared
INCOMPLETE.
Sets expectation for the number of errors.
Testcase start.
Waiting for the reset to complete; the reset is asserted in a
separate initial block.
Sets the number of packets to be sent to the regular data
port of the DUT MegaCore function.
Sets the number of packets to be sent to the high priority
port of the DUT MegaCore function.
Sets the number of packets to be sent to the regular data
port of the SISTER MegaCore function.
Sets the number of packets to be sent to the high priority
port of the SISTER MegaCore function.
Wait for DUT and SISTER to go into link-up.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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