参数资料
型号: IP-SLITE2
厂商: Altera
文件页数: 55/110页
文件大小: 0K
描述: IP SERIALLITE II
标准包装: 1
系列: *
类型: MegaCore
功能: SerialLite II 协议
许可证: 初始许可证
4. Functional Description
The SerialLite II MegaCore function consists of parameterized logic and a
parameterized testbench. The following sections detail the various possible
configurations and things you should consider when deciding how to configure the
link. Figure 4–1 shows a block diagram of the SerialLite II MegaCore function.
f Refer to Chapter 5, Testbench for more information on the test bench.
Figure 4–1. SerialLite II MegaCore Function Block Diagram
SerialLite II MegaCore Function
Atlantic
Interface
Data
Flo w
Atlantic
Interface
Data
Flo w
Link Layer
Recei v er
Transmitter
PHY Layer (PCS)
n-bit
n-bit
W ord Aligner
Training Detection
& Generator
Link State Machine
n-bit
n-bit
SERDES
SERDES
SERDES
SERDES
SerialLite II
Interface
SerialLite II
Interface
As shown in Figure 4–1 , the SerialLite II MegaCore function is divided into two main
blocks: a protocol processing portion (data link layer) and a high-speed front end
(physical layer). The protocol processing portion features Atlantic FIFO buffers for
data storage or clock domain crossing, as well as data encapsulation and extraction
logic. The high-speed front end contains a link state machine (LSM) and
serializer/deserializer (SERDES) blocks. The SERDES blocks contain optional high-
speed serial clock and data recovery (CDR) logic implemented with high-speed serial
transceivers.
Interface Overview
The SerialLite II MegaCore function has two interfaces, the Atlantic interface and a
high-speed serial interface.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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