参数资料
型号: IP-SLITE2
厂商: Altera
文件页数: 78/110页
文件大小: 0K
描述: IP SERIALLITE II
标准包装: 1
系列: *
类型: MegaCore
功能: SerialLite II 协议
许可证: 初始许可证
4–24
Chapter 4: Functional Description
Signals
Table 4–6. Transceiver Megafunction Signals (Part 2 of 3)
Signal
(1) , (2)
Direction
Clock Domain
Description
err_tc_pcfifo_uflw
[tx n l- 1:0 ]
err_tc_pcfifo_oflw
[tx n l- 1:0 ]
stat_rr_sigdet
[ r x n l- 1:0 ]
Output
Output
Output
tx_coreclock
tx_coreclock
rrefclk
Interface/phase compensation FIFO buffer
underflow signal (Arria II GX and Stratix IV devices
only).
Interface/phase compensation FIFO buffer overflow
signal (Arria II GX and Stratix IV devices only).
This signal is for debugging purposes only and can
be ignored.
stat_rr_gxsync
[ sr x- 1:0 ]
Output
rrefclk
Gives the status of the pattern detector and word
aligner.
Receiver PLL locked signal. Indicates whether or
not the receiver PLL is phase locked to the CRU
reference clock. When the PLL locks to data, which
stat_rr_rxlocked
[ r x n l- 1:0 ]
Output
rrefclk
happens some time after the transceiver’s
rx_freqlocked signal is asserted high, this signal
has little meaning because it only indicates lock to
the reference clock. This signal is active high for
Arria II GX and Stratix IV devices.
stat_rr_freqlock
[ r x n l-1:0]
stat_rr_pattdet
[ sr x-1:0]
Output
Output
rrefclk
rrefclk
Frequency locked signal from the CRU. Indicates
whether the transceiver block receiver channel is
locked to the data mode in the rxin port.
Pattern detection signal
ALTGX Reconfig from the GXB Bus.
reconfig_fromgxb
This signal is connected to the reconfig_fromgxb
Arria II GX or Stratix IV GX:
[recon_quad*17-1:0]
Output
reconfig_clk
port on the altgx_reconfig module. If you use
Arria II GX or Stratix IV device, you must connect
this output to the altgx_reconfig module for
offset cancelation.
ALTGX Reconfig to the GXB Bus.
reconfig_togxb
This signal is connected to the reconfig_togxb
Arria II GX or Stratix IV GX:
[3:0]
Input
reconfig_clk
port on the altgx_reconfig module. If you use
Arria II GX or Stratix IV device, you must connect
this output to the altgx_reconfig module for
offset cancelation.
ALTGX Reconfig Clock to the GXB.
This signal is connected to the reconfig_clk port
reconfig_clk
Input
on the altgx_reconfig module. If you use
Arria II GX or Stratix IV device, you must connect
this output to the altgx_reconfig module for
offset cancelation.
Calibration clock for the termination resistor
cal_blk_clk
Input
calibration block. The frequency range of
cal_blk_clk is 10 to 125 MHz.
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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