参数资料
型号: IP-SLITE2
厂商: Altera
文件页数: 67/110页
文件大小: 0K
描述: IP SERIALLITE II
标准包装: 1
系列: *
类型: MegaCore
功能: SerialLite II 协议
许可证: 初始许可证
Chapter 4: Functional Description
Clocks and Data Rates
Figure 4–12. Full Featured Clock Structure for 5G Symmetrical With TSIZE = 2
slite2_top
rc v d_clk_out[n-1:0]
4–13
rxrdp_clk
tx_coreclock
tx_coreclk
Atlantic
Regular
ATLFIFO
tx_coreclock
W ord Aligner (&
Training Pattern
n-bit
PComp_
FIFO_0
RM_
FIFO_0
Byte
deserializer
RX Core
Detection),
[Link State
Machine]
#n SLITE2
High
Speed
Atlantic
Priority
PComp_
RM_
Byte
Links
rxhpp_clk
ATLFIFO
tx_coreclock
n-bit
FIFO_n-1
FIFO_n-1
deserializer
rc v d_clkn-1
Atlantic
Regular
txrdp_clk
ATLFIFO
tx_coreclock
Training
n-bit
Byte
serializer
#m SLITE2
Generator [Link
State Machine]
High
Speed
TX Core
Byte
Links
tx_coreclock
n-bit
serializer
Atlantic
Priority
txhpp_clk
ATLFIFO
TXPLL
XC V R
Reset Sync
tx_coreclock
mreset_n
trefclk
Arria V, Cyclone V, and Stratix V Transceiver Clocking
For Arria V, Cyclone V, and Stratix V configurations, you must integrate the
transceiver to the SerialLite II MegaCore function manually.
When you configure the transceiver to work in more than 1 lane per SerialLite II
instance, the tx_clkout(0) signal from the TX channel (PHY IP) must drive the
SerialLite II input clock ( tx_coreclk ) and the input port ( tx_coreclkin ) of all TX
channels (PHY IP). Similarly, if your design requires more than 1 RX channel per
SerialLite II instance, the rx_clkout(0) from the RX channel (PHY IP) must drive the
SerialLite II input clock ( rx_coreclk ) and the input port ( rx_coreclkin ) of all RX
channels (PHY IP).
SerialLite II MegaCore Pin-Out Diagrams
This section shows pin-out diagrams for the SerialLite II MegaCore function. The
following diagrams are included:
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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