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参数资料
| 型号： | IR3500VMTRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 13/34页 |
| 文件大小： | 0K |
| 描述： | IC XPHASE3 CTLR VR11.1 32-MLPQ |
| 标准包装： | 1 |
| 系列： | XPhase3™ |
| 应用： | 处理器 |
| 电流 - 电源： | 6.5mA |
| 电源电压： | 4.75 V ~ 7.5 V |
| 工作温度： | 0°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-MLPQ（5x5） |
| 包装： | 标准包装 |
| 其它名称： | IR3500VMTRPBFDKR |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
IR3500V
SS CLEARED
POWER NOT OK
VCCL
ENABLE
VBIAS
INTEL
ENABLE
COMPARATOR
-
+
250nS
BLANKING
OC after VRRDY
DISABLE
VID FAULT
1
FAULT LATCH1 FAULT LATCH1 2
FAULT LATCH2 3
OV FAULT 4
400K
VCCLDRV
6
PGOOD
AMD 1.2V
VCCLDRV
VCCLFB
850mV
800mV 1.14V
VCCL REGULATOR
AMPLIFIER
80mV
120mV
4.0V
DELAY POWER OK
COMPARATOR LATCH
DISCHARGE R
COMPARATOR
S Q
RESET
DOMINANT
OC DELAY
RESET
OC
VID FAULT LATCH
VCCL UVLO
OC before VRRDY
IROSC
OC DELAY
PHSOUT
COUNTER
S Q
SET
DOMINANT
SS RESET
R
UV CLEARED
FAULT LATCH2
UV 5
VRHOT COMPARATOR
-
+
HOTSET
VRHOT
SS RESET
VCCL OUTPUT
1.19V 0.94 +
0.86 COMPARATOR
VCCL UVLO
Voltage
0.86
VIDSEL
VIDSEL
3.3V
VIDSEL
VID
3.5k 1.3uS
BLANKING
VIDSEL
DIGITAL
VIDSEL VBOOT
VID7 INPUT
VID
TO ANALOG
LATCH
VID SAMPLE
VID5
VBOOT
(1.1V) Q
VIDSEL
VID4
VID3
VID3
INTERNAL
VID2
VID1 AMD 1.0V
VID1
VID0 INTEL 0.6V
VID0
1.6V
COMPARATOR
1.5V
OV@START
OC LIMIT
OC LIMIT
AMPLIFIER
ISETPT
COMPARATOR DETECTION
LATCH
OV@OPERATION
OV FAULT
UNDER
+
VOLTAGE
275mV
VCCL UVLO
315mV COMPARATOR
R
1.73V COMPARATOR
OV@START
SS/DEL
VIDSEL
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
CLKOUT
VIDSEL
COMPARATORS DOMINANT
VID6
COMPARATORS VID6
(1/8 SHOWN) S DELAY
VID4
VCCL UVLO
VID0
CLKOUT
AMD 5-BIT
AMD 6-BIT
VR11 BOOT
VR11 NoBOOT
VID7
VID5
CONVERTER
VDAC
VID2 DVID
FAULT
OPEN DAISY
-
LATCH
FAULT
VBOOT SET COMPARATOR
S
R Q
8-Pulse
Delay
0.2V 1.08V
VCCL
-
EAOUT
+
VID FAULT
Float 0.6V LATCH
R Q
SET
S
FAULT LATCH1
FAULT LATCH2
DOMINANT
SAMPLE DELAY
R
OV FAULT 3.2V
DYNAMIC VID DETECT
OPEN SENSE LINE
COMPARATOR
IDCHG
4.5uA
OVER
130mV VOLTAGE OV FAULT
3mV
-
VDAC
OPEN VOLTAGE LOOP S Q VCCL
SET
DOMINANT
VCCL UVLO
R OV@OPERATION
IROSC
IOCSET
SOFT
DIS START 1.4V
CLAMP
PULSE
UV
25k
OPEN DAISY CHAIN 1.6V
VDRP AMPLIFIER
ERROR
AMPLIFIER
DISABLE
IROSC
S Q
SET
DOMINANT
VO POWER-UP OV
-
IIN
OCSET
VDRP
EAOUT
FB
VSETPT
PHSIN
IVOSEN+ IVOSEN-
VIDSEL
IVOSEN-
LINE DETECT
PHSOUT
PHSIN
LGND
PHSOUT
VCCL-1.2V
0.6V
IROSC
OV@OPERATION
VCCLDRV
CHAIN
ROSC BUFFER
AMPLIFIER
IROSC
CURRENT
SOURCE
50mV
VDAC BUFFER
AMPLIFIER
ISOURCE
ISINK
60mV
OPEN SENSE
LINE DETECT
COMPARATORS
25k
VO
25k
25k
REMOTE SENSE
AMPLIFIER DETECTION
PULSE
RESET
VCCL VCCL
+
OPEN SENSE
VOSEN+
VOSEN-
GENERATOR
COMPARATORS
OV@START
-
+
-
VCCL*0.9
ROSC/OVP
VDAC
VO
200mV
OPEN SENSE LINE
+
ENABLE 0.4V
-
+
Figure 8 – IR3500V Block Diagram
VID Control
The VID pins require an external bias voltage and should not be floated. The VID input comparators monitor the VID
pins and control the Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The
output of the buffer amplifier is the VDAC pin. The VDAC voltage, input offsets of error amplifier and remote sense
differential amplifier are post-package trimmed to provide 0.7% system set-point accuracy. The actual VDAC
voltage does not directly determine the system accuracy, which has a wider tolerance.
The IR3500V can accept changes in the VID code while operating and vary the DAC voltage accordingly. The slew
rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and LGND pin. A
resistor connected in series with this capacitor is required to compensate the VDAC buffer amplifier. Digital VID
transitions result in a smooth analog transition of the VDAC voltage and converter output voltage minimizing inrush
currents in the input and output capacitors and overshoot of the output voltage.
Page 13 of 34
July 28, 2008
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| IR3502AMTRPBF | 功能描述:IC XPHASE CTRL VR11.0/1 32-MLPQ RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:XPhase3™ 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
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