参数资料
型号: IR3500VMTRPBF
厂商: International Rectifier
文件页数: 23/34页
文件大小: 0K
描述: IC XPHASE3 CTLR VR11.1 32-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 6.5mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
其它名称: IR3500VMTRPBFDKR
IR3500V
Open Remote Sense Line Protection
If either remote sense line VOSEN+ or VOSEN- or both are open, the output of remote sense amplifier (VO) drops.
The IR3500V monitors VO pin voltage continuously. If VO voltage is lower than 200 mV, two separate pulse
currents are applied to VOSEN+ and VOSEN- pins respectively to check if the sense lines are open. If VOSEN+ is
open, a voltage higher than 90% of V(VCCL) will be present at VOSEN+ pin and the output of open line detect
comparator will be high. If VOSEN- is open, a voltage higher than 700mV will be present at VOSEN- pin and the
output of open-line-detect comparator will be high. The open sense line fault latch is set, which pulls the error
amplifier output low immediately and shut down the converter. The SS/DEL voltage is discharged and the fault latch
can only be reset by cycling VCCL power.
Open Daisy Chain Protection
IR3500V checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and
detects the feedback at PHSIN pin. If no pulse comes back after 32 CLKOUT pulses, the pulse is restarted again. If
the pulse fails to come back the second time, the open daisy chain fault is registered, and SS/DEL is not allowed to
charge. The fault latch can only be reset by cycling the power to VCCL.
After powering up, the IR3500V monitors PHSIN pin for a phase input pulse equal or less than the number of
phases detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is
started on PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an open daisy chain fault
is registered.
Phase Number Determination
After a daisy chain pulse is started, the IR3500V checks the timing of the input pulse at PHSIN pin to determine the
phase number. This information is used to have symmetrical phase delay between phase switching without the
need of any external component.
Single Phase Operation
In an architecture where only a single phase is needed the switching frequency is determined by the clock
frequency.
Fault Operation Table
The Fault Table shown in figure 20 describes the different faults that can occur and how IR3500V will react to
protect the supply and the load from possible damage. The fault types that can occur are listed in row 1. Row 2 has
the method that a fault is cleared. The first 5 faults are latched in the UV fault latch and the VCCL power has to be
recycled by switching off the input and switching it back on for the converter to work again. The rest of the faults
(except for UVLO Vout) are latched in the SS fault latch and do not require the VCCL power to be recycled in order
to resume normal operation once the fault condition clears. Most of the faults disable the error amplifier (EA) and
discharge the soft start capacitor. All the faults flag PGOOD. PGOOD returns back to high when the faults are
cleared. The delay row shows reaction time after detecting a fault condition. Delays are provided to minimize the
possibility of nuisance faults.
Page 23 of 34
July 28, 2008
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