参数资料
型号: IR3500VMTRPBF
厂商: International Rectifier
文件页数: 26/34页
文件大小: 0K
描述: IC XPHASE3 CTLR VR11.1 32-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 6.5mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
其它名称: IR3500VMTRPBFDKR
IR3500V
R OCSET = [
I LIMIT
n
? R L _ MAX ? ( 1 + K P ) + V CS _ TOFST ] ? G CS / I OCSET
(12)
? V I ? D ? ( 1 ? D ) ? n ? ( D ? n ) ? ( n
K P = ?
? D ) ?
? m  m + 1 ?
( I LIMIT / n ) ? L ? f sw ? 2 ? D ? ( 1 ? D )
?
(13)
Where; I LIMIT =Over current limit, n=Number of phases, K P =Ratio of the peak to average current for the inductor,
G CS =Gain of the current sense amplifier, I OCSET = Determined by the ROSC and given by Figure 10,
D=Vo/V I , m=Maximum integer that doesn’t exceed (n*D)
No Load Output Voltage Setting Resistor R VSETPT ,
A resistor between VSETPT pin and VDAC is used to create output voltage offset V O_NLOFST, which is the
difference between V DAC voltage and output voltage at no load condition. R VSETPT is determined by (14), where
I VSETPT is the current flowing out of VSETPT pin as shown in Figure 23.
R VSETPT =
V O _ NLOFST
I VSETPT
(14)
VCCL Capacitor C VCCL
The capacitor is selected based on the stability requirement of the linear regulator and the load current to be
driven. The linear regulator supplies the bias and gate drive current of the phase ICs. A 4.7uF normally ensures
stable VCCL performance.
VCCL Programming Resistor R VCCLFB1 and R VCCLFB2
Since VCCL voltage is proportional to the MOSFET gate driver loss and inversely proportional to the
MOSFET conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. VCCL
linear regulator consists of an external NPN transistor, a ceramic capacitor and a programmable resistor
divider. Pre-select R VCCLFB1 , and calculate R VCCLFB2 from (15).
R VCCLFB 2 =
R VCCLFB 1 * 1. 19
VCCL ? 1 . 19
(15)
VCCL Regulator Drive Resistor R VCCLDRV
The drive resistor is primarily dependent on the load current requirement of the linear regulator and the
minimum input voltage requirements. The following equation gives an estimate of the average load current of
the switching phase ICs.
I drive _ avg = [ ( Q gb + Q gt ) ? f sw + 10 mA ] ? n
(16)
Q gb and Q gt are the gate charge of the top and bottom FET. For a minimum input voltage and a maximum
VCCL, the maximum R VCCLDRV required to use the full pull-down current of the VCCL driver is given by
R VCCLDRV =
V I (min) ? 0.7 ? VCCL (max)
I drive _ avg / β min
(17)
Due to limited pull down capability of the VCCLDRV pin, make sure the following condition is satisfied.
Page 26 of 34
July 28, 2008
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