参数资料
型号: IR3500VMTRPBF
厂商: International Rectifier
文件页数: 24/34页
文件大小: 0K
描述: IC XPHASE3 CTLR VR11.1 32-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 6.5mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-MLPQ(5x5)
包装: 标准包装
其它名称: IR3500VMTRPBFDKR
IR3500V
Fault Type
Open
Daisy
Open
Control
Loop
Open
Sense
Line
Over
Voltage
VID
Disable
VCCL
UVLO
OC Before
Start-up
OC After
Start-up
VOUT
UVLO
Fault
Clearing
Method
Error Amp
Disabled
ROSC/OVP
& IIN drive
Recycle VCCL
Yes
Resume Normal Operation when Condition Clears
No
high until
No
Yes
No
OV clears
SS/DEL
Discharge
Flags
PGood
Yes
Yes
PHSOUT
No
Delay?
32 Clock
Pulses
8
PHSOUT
Pulses
No
No
1.3us
Blank
Time
250 ns
Blank
Time
No
Pulses. Count
Programmed by
ROSC value
SS/DEL
Discharge
Threshold
No
Figure 20 – Fault Table
APPLICATIONS INFORMATION
DESIGN PROCEDURE
Oscillator Resistor Rosc
The oscillator of IR500 generates square-wave pulses to synchronize the phase ICs. The switching frequency of
each phase converter equals the PHSOUT frequency, which is set by the external resistor R OSC according to the
curve in Figure 23. The CLKOUT frequency equals the switching frequency multiplied by the phase number. The
Rosc sets the reference current used for the no load offset and OCSET which is given by Figure 5 and equals:
ISETPT = IOCSET =
0 . 595
Rosc
(1)
Soft Start Capacitor C SS/DEL
The soft start capacitor C SS/DEL programs five different time parameters. They include soft start delay time, soft
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 12. After the
ENABLE pin voltage rises above 0.85V, there is a soft-start delay time TD1 , after which the error amplifier output
is released to allow the soft start of output voltage. The soft start time TD2 represents the time during which
converter voltage rises from zero to 1.1V . The VID sample delay time (TD3) is the time period when VID stays at
boot voltage of 1.1V. VID rise or fall time (TD4) is the time when VID changes from boot voltage to the final
voltage. The VR ready delay time (TD5) is the time period from VR reaching the final voltage to the VR ready
signal being issued, which is determined by the delay comparator threshold.
C SS/DEL = 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
TD 1 =
C SS / DEL * 1. 4
I CHG
=
C SS / DEL * 1.4
52 . 5 * 10 ? 6
(2)
Page 24 of 34
July 28, 2008
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