参数资料
| 型号： | ISL6322IRZ |
| 厂商： | Intersil |
| 文件页数： | 14/41页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6322
? ------------- + 1 ?
( R 1 ? R 2 )
V C ( s ) = -------------------------------------------------------- ? K ? DCR ? I L
R 2
s ? L
? DCR ?
? ?
? s ? ------------------------ ? C + 1 ?
? R 1 + R 2 ?
K = ---------------------
R 2 + R 1
(EQ. 5)
(EQ. 6)
decreases to 0A as the voltage at the VID pin varies from 0
to the internal 1.2V pull-up voltage. In AMD modes of
operation the VID pins are pulled low by a weak 20 μ A
current source. External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to
a voltage of 5V.
The ISL6322 accommodates four different DAC ranges: Intel
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time
constant, then V C is equal to the voltage drop across the
DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1 .
VR10 (Extended), Intel VR11, AMD K8/K9 5-bit, and AMD
6-bit. The state of the VRSEL and VID7 pins decide which
DAC version is active. Refer to Table 1 for a description of
how to select the desired DAC version.
TABLE 1. ISL6322 DAC SELECT TABLE
UGATE(n)
V IN
I
L
DAC VERSION
VR10(Extended)
VRSEL PIN
VRSEL < 0.6V
VID7 PIN
-
MOSFET
L
DCR
V OUT
VR11
0.8V < VRSEL < 3.0V
-
DRIVER
LGATE(n)
INDUCTOR
V L (s)
C OUT
AMD 5-Bit
AMD 6-Bit
3.0V < VRSEL < VCC
3.0V < VRSEL < VCC
low
high
V C (s)
R 1
C
TABLE 2. VR10 (EXTENDED) VOLTAGE IDENTIFICATION
CODES
ISL6322 INTERNAL CIRCUIT
I n
SAMPLE
R 2*
VID4
0
0
0
0
VID3
1
1
1
1
VID2
0
0
0
0
VID1
1
1
1
1
VID0
0
0
1
1
VID5
1
1
0
0
VID6
1
0
1
0
VDAC
1.60000
1.59375
1.58750
1.58125
+
-
V C (s)
ISEN-(n)
0
0
1
1
0
0
1
1
1
1
1
1
1
0
1.57500
1.56875
I SEN
R ISEN
ISEN+(n)
*R 2 is OPTIONAL
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1.56250
1.55625
1.55000
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
The capacitor voltage V C , is then replicated across the
sense resistor R ISEN . The current through R ISEN is
proportional to the inductor current. Equation 7 shows that
the proportion between the channel current and the sensed
current (I SEN ) is driven by the value of the sense resistor,
the resistor divider ratio, and the DCR of the inductor.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
I SEN = K ? I L ? ------------------
DCR
R ISEN
(EQ. 7)
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1.50000
1.49375
1.48750
Output Voltage Setting
The ISL6322 uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the VID pins. The DAC decodes the logic signals into one of
the discrete voltages shown in Tables 2, 3, 4 and 5. In Intel
modes of operation, each VID pin is pulled up to an internal
1.2V voltage by a weak current source (40 μ A), which
0
0
0
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
1
0
1
0
1.48125
1.47500
1.46875
1.46250
1.45625
14
FN6328.2
August 2, 2007
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