参数资料
| 型号： | ISL6322IRZ |
| 厂商： | Intersil |
| 文件页数： | 21/41页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6322
Output-Voltage Offset Programming
The ISL6322 allows the designer to accurately adjust the
FB
offset voltage by connecting a resistor, R OFS , from the OFS
pin to VCC or GND. When R OFS is connected between OFS
+
V OFS
-
R FB
I OFS
E/A
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into the FB pin.
VDIFF
VCC
REF
If R OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I OFS flows out of the FB pin. The
offset current flowing through the resistor between VDIFF
and FB will generate the desired offset voltage which is
equal to the product (I OFS x R FB ). These functions are
shown in Figures 7 and 8.
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
1:1
CURRENT
MIRROR
I OFS
+
0.4V
For Negative Offset (connect R OFS to GND):
OFS
-
R OFS = --------------------------
0.4 ? R FB
V OFFSET
(EQ. 12)
R OFS
GND
ISL6322
GND
For Positive Offset (connect R OFS to VCC):
FIGURE 8. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
R OFS = --------------------------
1.6 ? R FB
V OFFSET
FB
(EQ. 13)
INTEL DYNAMIC VID TRANSITIONS
When in Intel VR10 or VR11 mode, the ISL6322 checks the
VID inputs on the positive edge of an internal 3MHz clock. If
a new code is established and it remains stable for 3
consecutive readings (1 μ s to 1.33 μ s), the ISL6322
-
V OFS
+
R FB
I OFS
E/A
recognizes the new code and changes the internal DAC
reference directly to the new level. The Intel processor
VDIFF
1:1
CURRENT
MIRROR
REF
controls the VID transitions and is responsible for
incrementing or decrementing one VID step at a time. In
VR10 and VR11 settings, the ISL6322 will immediately
change the internal DAC reference to the new requested
VCC
I OFS
value as soon as the request is validated, which means the
fastest recommended rate at which a bit change can occur is
once every 2 μ s. In cases where the reference step is too
large, the sudden change can trigger overcurrent or
overvoltage events.
R OFS
OFS
ISL6322
-
1.6V
+
In order to ensure the smooth transition of output voltage
during a VR10 or VR11 VID change, a VID step change
smoothing network is required. This network is composed of
an internal 1k Ω resistor between the DAC and the REF pin,
VCC
FIGURE 7. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6322
and the external capacitor C REF , between the REF pin and
ground. The selection of C REF is based on the time duration
for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1 bit every T VID , the relationship between C REF and T VID is
given by Equation 14.
to do this by making changes to the VID inputs. The ISL6322
C REF = 0.001 ( S ) ? T VID
(EQ. 14)
is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner, supervising a
safe output voltage transition without discontinuity or
disruption. The DAC mode the ISL6322 is operating in
determines how the controller responds to a dynamic VID
change.
21
As an example, for a VID step change rate of 5 μ s per bit, the
value of C REF is 5600pF based on Equation 14.
FN6328.2
August 2, 2007
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