参数资料
| 型号： | ISL6322IRZ |
| 厂商： | Intersil |
| 文件页数： | 35/41页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6322
COMPENSATION WITH LOAD-LINE REGULATION
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
Once selected, the compensation values in Equation 41
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from the
case equations in Equation 41 unless some performance
issue is noted.
-------------------------------- > f 0
compensation components, R C and C C .
C 2 (OPTIONAL)
Case 1:
1
2 ? π ? L ? C
R C = R FB ? --------------------------------------------------------
2 ? π ? V PP ? R FB ? f 0
R C
C C
COMP
2 ? π ? f 0 ? V pp ? L ? C
0.66 ? V IN
0.66 ? V IN
C C = ----------------------------------------------------
FB
ISL6322
-------------------------------- ≤ f 0 < -------------------------------------
V PP ? ( 2 ? π ) 2 ? f 02 ? L ? C
R C = R FB ? -----------------------------------------------------------------
R FB
IDROOP
VDIFF
Case 2:
1 1
2 ? π ? L ? C 2 ? π ? C ? ESR
0.66 ? V IN
(EQ. 41)
( 2 ? π ) 2 ? f 02 ? V PP ? R FB ? L ? C
FIGURE 23. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6322 CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
0.66 ? V IN
C C = -------------------------------------------------------------------------------------
f 0 > -------------------------------------
R C = R FB ? ---------------------------------------------
2 ? π ? V PP ? R FB ? f 0 ? L
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f 0 .
Case 3:
1
2 ? π ? C ? ESR
2 ? π ? f 0 ? V pp ? L
0.66 ? V IN ? ESR
0.66 ? V IN ? ESR ? C
C C = ----------------------------------------------------------------
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f 0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equation 41:
- L is the per-channel filter inductance divided by the
number of active channels,
- C is the sum total of all output capacitors,
- ESR is the equivalent series resistance of the bulk output
filter capacitance, and
- V PP is the peak-to-peak sawtooth signal amplitude as
35
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 23). Keep
a position available for C 2 , and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
FN6328.2
August 2, 2007
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