参数资料
| 型号： | ISL6322IRZ |
| 厂商： | Intersil |
| 文件页数： | 20/41页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页
ISL6322
Voltage Regulation
The integrating compensation network shown in Figure 6
EXTERNAL CIRCUIT
ISL6322 INTERNAL CIRCUIT
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
COMP
VID DAC
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6322 to include the
combined tolerances of each of these elements.
The output of the error amplifier, V COMP , is compared to the
C C
R C
REF
C REF
1k
ERROR
+
triangle waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
FB
AMPLIFIER
-
V COMP
and regulate the converter output so that the voltage at FB is
I OFS
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 8. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 6.
(EQ. 8)
V OUT = V REF – V OFS – V DROOP
R FB
IDROOP
+
(V DROOP + V OFS )
-
VDIFF
I AVG
The ISL6322 incorporates an internal differential remote-
V OUT +
VSEN
+
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
V OUT -
RGND
-
voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the
non-inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V DIFF , is
connected to the inverting input of the error amplifier through
an external resistor.
Load-Line (Droop) Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of output
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
As shown in Figure 6, a current proportional to the average
current of all active channels, I AVG , flows from FB through a
load-line regulation resistor R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined in Equation 9:
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
V DROOP = I AVG ? R FB
(EQ. 9)
the output voltage can effectively be level shifted in a
direction which works to achieve the load-line regulation
required by these manufacturers.
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equation 9 with Equation 10.
V OUT = V REF – V OFS – ? ------------- ? ? R FB ?
? I OUT DCR ?
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
? N R ISEN ?
------------------
(EQ. 10)
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
In Equation 10, V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the internal sense resistor
connected to the ISEN+ pin, and R FB is the feedback
resistor, N is the active channel number, and DCR is the
Inductor DCR value.
Therefore the equivalent load-line impedance, i.e. droop
impedance, is equal to Equation 11:
R LL = ------------ ? ------------------
R ISEN
crossing the upper specification limit.
20
R FB DCR
N
(EQ. 11)
FN6328.2
August 2, 2007
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6323AIRZ | IC PWM CTRLR SYNC BUCK DL 48QFN |
| ISL6323BIRZ | IC PWM CTRLR SYNC BUCK DL 48QFN |
| ISL6323IRZ | IC HYBRID CTRLR PWM MONO 48-QFN |
| ISL6324AIRZ | IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324IRZ | IC HYBRID CTRLR PWM DUAL 48-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6322IRZ-T | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6323ACRZ | 功能描述:IC PWM CTRLR SYNC BUCK DL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6323ACRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONT. FOR CORE+NORTHBRIDGE,1 PHASE PSI, 3.4MHZ SVI - Rail/Tube 制造商:Intersil Corporation 功能描述:IC PWM CTRLR SYNC BUCK DL 48QFN |
| ISL6323ACRZ-T | 功能描述:IC PWM CTRLR SYNC BUCK DL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6323ACRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE+NORTHBRIDGE,1 PHASE PSI,3.4MHZ SV - Tape and Reel 制造商:Intersil Corporation 功能描述:IC PWM CTRLR SYNC BUCK DL 48QFN |
发布紧急采购，3分钟左右您将得到回复。