参数资料
| 型号： | ISL6322IRZ |
| 厂商： | Intersil |
| 文件页数： | 24/41页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6322
For the Intel VR10 and VR11 modes of operation, the
soft-start sequence is composed of four periods, as shown in
Figure 11. Once the ISL6322 is released from shutdown and
After this delay period, the VR will begin first soft-start ramp
until the output voltage reaches 1.1V VBOOT voltage. Then,
the controller will regulate the VR voltage at 1.1V for another
fixed period TD3. At the end of TD3 period, ISL6322 will
read the VID signals. If the VID code is valid, ISL6322 will
initiate the second soft-start ramp until the output voltage
reaches the VID voltage plus/minus any offset or droop
voltage.
NOTE: If the SS pin is grounded, the soft-start ramp in TD2
and TD4 will be defaulted to a 6.25mV step frequency of
330kHz.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TD5. The typical value
for TD5 is 440μs.
VOUT, 500mV/DIV
The soft-start time is the sum of the four periods as shown in
Equation 17.
(EQ. 17)
T SS = TD1 + TD2 + TD3 + TD4
TDA
EN_VTT
TDB
TDC
PGOOD
VOUT, 500mV/DIV
500μs/DIV
FIGURE 12. AMD SOFT-START WAVEFORMS
AMD Soft-Start
TD1
TD2
TD3 TD4
TD5
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of three periods, as shown
EN_VTT
PGOOD
500μs/DIV
FIGURE 11. INTEL SOFT-START WAVEFORMS
TD1 is a fixed delay with the typical value as 1.40ms. TD3 is
in Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period TDA. After this delay period the ISL6322 will
begin ramping the output voltage to the desired DAC level at
a fixed rate of 6.25mV per step, with a stepping frequency of
330kHz. The amount of time required to ramp the output
voltage to the final DAC voltage is referred to as TDB, and
can be calculated as shown in Equation 20.
TDB = -------------------------- ? ? --------------------- ?
3 ? 0.00625 ?
determined by the fixed 85μs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
330 × 10
1 V VID
(EQ. 20)
Therefore the minimum TD3 is about 86μs.
During TD2 and TD4, ISL6322 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R SS from SS pin to GND. The
second soft-start ramp time TD2 and TD4 can be calculated
based on the following equations:
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay TDC. The typical value
for TDC can range between 1.5ms and 3.0ms.
1.1 ? R SS
6.25 ? 25
( V VID – 1.1 ) ? R SS
6.25 ? 25
TD2 = ------------------------ ( μ s )
TD4 = ---------------------------------------------------- ( μ s )
(EQ. 18)
(EQ. 19)
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time TD2 will be 704μs and
the second soft-start ramp time TD4 will be 256μs.
24
FN6328.2
August 2, 2007
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