参数资料
| 型号： | ISL6322IRZ |
| 厂商： | Intersil |
| 文件页数： | 32/41页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 4PHASE BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6322
? I M ?
I PP
P UP , 4 ≈ r DS ( ON ) ? d ? ? ------ ? + ----------
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
? N ? 12
2 2
(EQ. 28)
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I M , V D(ON) , the switching
frequency, f S , and the length of dead times, t d1 and t d2 , at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results from
Equations 25, 26, 27 and 28. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
? ? ------ + I ---------- ? ? t
? I ?
? I
?
+ ? ------ – ---------- ? ? t
M
PP
? N 2 ?
P
LOW , 2
= V
D ( ON )
? f
S
M PP
? N 2 ?
d1
I
? ?
d2
(EQ. 24)
solutions to the loss equations for different MOSFETs and
different switching frequencies.
Package Power Dissipation
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P LOW,1 and P LOW,2 .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the
upper-MOSFET losses are due to currents conducted
across the input voltage (V IN ) during switching. Since a
substantially higher portion of the upper-MOSFET losses are
dependent on switching frequency, the power calculation is
more complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode
reverse-recovery charge, Q rr , and the upper MOSFET
r DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 25,
the required time for this commutation is t 1 and the
approximated associated power loss is P UP,1 .
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three drivers
in the controller package, the total power dissipated by all three
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 38 for
thermal transfer improvement suggestions.
When designing the ISL6322 into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P Qg_TOT , due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 29 and 30, respectively.
P UP , 1 ≈ V IN ? ? ------ + --------- ?
? ? ---- 1 ? ? f S
? N 2 ?
I M I PP
? t ?
? 2 ?
(EQ. 25)
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
(EQ. 29)
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 26, the
approximate power loss is P UP,2 .
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
P UP , 2 ≈ V IN ? ? ------ – --------- ? ? ? ---- 2 ? ? f S
I DR = ? --- ? Q G1 ? N
? I M I PP ? ? t ?
? N 2 ? ? 2 ?
(EQ. 26)
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
(EQ. 30)
A third component involves the lower MOSFET
reverse-recovery charge, Q rr . Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q rr , it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P UP,3 .
In Equations 29 and 30, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power loss;
the gate charge (Q G1 and Q G2 ) is defined at the particular gate
to source drive voltage PVCC in the corresponding MOSFET
data sheet; I Q is the driver total quiescent current with no load
at both drive outputs; N Q1 and N Q2 are the number of upper
P UP , 3 = V IN ? Q rr ? f S
(EQ. 27)
and lower MOSFETs per phase, respectively; N PHASE is the
number of active phases. The I Q* VCC product is the quiescent
Finally, the resistive part of the upper MOSFET is given in
Equation 28 as P UP,4 .
32
power of the controller without capacitive load and is typically
75mW at 300kHz.
FN6328.2
August 2, 2007
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