参数资料
型号: ISL8121IRZ
厂商: Intersil
文件页数: 12/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 2MHz
占空比: 66%
电源电压: 4.9 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-VFQFN 裸露焊盘
包装: 管件
ISL8121
SETTING THE OUTPUT VOLTAGE
OUTPUT CURREN T
EN
The ISL8121 uses a precision internal reference voltage
to set the output voltage. Based on this internal
reference, the output voltage can thus be set from 0.6V
up to a level determined by the input voltage, the
GND>
SS
maximum duty cycle, and the conversion efficiency of
the circuit. Equation 7 estimates this maximum
amplitude the output voltage can be regulated to.
V OUTMAX = d MAX ? V IN ? Efficiency
(EQ. 7)
Obviously, ensure that the input voltage and all the
voltages sampled by the ISL8121 do not exceed the
GND>
OUTPUT VOLTAGE
controller’s absolute maximum limits, or any other limits
specified in this document.
FIGURE 6. OVERCURRENT BEHAVIOR WHILE IN
INTERNAL REFERENCE MODE
V REF
ISL8121
EXTERNAL CIRCUIT
As a result of an OC event, output drives turn off both
upper and lower MOSFETs, and the SS capacitor is
discharged via a 20μA current source. The behavior
ERROR
+
-
FB
following this standard response varies depending
whether the controller is operating in internal (using
internal reference; VMON > 3.5V) or external reference
AMPLIFIER
VDIFF
R 1
mode (using external reference; VMON < 3.5V). As
shown in Figure 6, the soft-start capacitor discharge
VSEN+
R S
+
prompted by the OC event is followed by two SS cycles,
during which the ISL8121 stays off. Following the
dormant SS cycles, the controller attempts to
X1
DIFFERENTIAL
+
-
VSEN-
R P
TO V OUT
-
re-establish the output. Should the OC condition been
removed, the output voltage is ramped up and operation
resumes as normal. Should the OC condition still be
present and result in another OC event, the entire
behavior repeats until the OC condition is removed or the
IC is disabled. Figure 7 details the OC behavior while in
external reference mode. Following the OC event, the
output drives are turned off, the ISL8121 latches off, and
the SS capacitor is discharged to ground. Resetting the
OC latch involves removal of bias power or cycling of the
AMPLIFIER
FIGURE 8. SETTING THE OUTPUT VOLTAGE AT THE
INPUT OF THE DIFFERENTIAL AMPLIFIER
The output voltage can be set via a simple resistor
divider, as shown in Figure 8. It is recommended this
resistor divider is connected at the input of the
differential amplifier (as this amplifier is powered from
the IC’s 5V bias and has limited input range).
R P = R ? -------------------------------------
R S = R ? ----------------
EN pin (pictured in Figure 7). Should the OC event been
removed, the controller initiates a new SS cycle and
restores the output voltage.
V OUT
V OUT – V REF
V OUT
V REF
(EQ. 8)
To avoid degradation of DC regulation tolerance due to
GND>
OUTPUT CURREN T
EN
the differential amplifier’s input resistance, a size
requirement is placed on the combined value of R P and
R S . Consider R to be the parallel combination of these
two resistors, and use a value of 2k Ω or less for R; use
the following equations to determine the value of R P and
R S , based on the desired out-put voltage, the reference
voltage, and the chosen value of R.
SS
GND>
OUTPUT VOLTAGE
FIGURE 7. OVERCURRENT BEHAVIOR WHILE IN
EXTERNAL REFERENCE MODE
12
FN6352.2
October 27, 2009
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