参数资料
型号: ISL8121IRZ
厂商: Intersil
文件页数: 21/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 2MHz
占空比: 66%
电源电压: 4.9 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-VFQFN 裸露焊盘
包装: 管件
ISL8121
L ≤ -------------------------------- ? ( Δ V MAX – Δ I ? ESR )
( Δ I )
2.5 ? C
L ≤ ----------------- ? ( Δ V MAX – Δ I ? ESR ) ? ( V IN – V O )
( Δ I )
4 ? C ? V OUT (EQ. 23)
2
While the previous equation addresses the leading edge,
the following equation gives the upper limit on L for
cases where the trailing edge of the current transient
causes a greater output voltage deviation than the
leading edge.
(EQ. 24)
2
Normally, the trailing edge dictates the selection of L, if
the duty cycle is less than 50%. Nevertheless, both
inequalities should be evaluated, and L should be
selected based on the lower of the two results. In all
equations in this paragraph, L is the per-channel
inductance and C is the total output bulk capacitance.
LAYOUT CONSIDERATIONS
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the
circuit and lead to device overvoltage stress. Careful
component layout and printed circuit design minimizes
the voltage spikes in the converter. Consider, as an
example, the turnoff transition of the upper PWM
MOSFET. Prior to turnoff, the upper MOSFET was carrying
channel current. During the turnoff, current stops flowing
in the upper MOSFET and is picked up by the lower
MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces
minimize the magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using a ISL8121 controller. The power
components are the most critical because they switch
large amounts of energy. Next are small signal
components that connect to sensitive nodes or supply
critical bypassing current and signal coupling.
Although the ISL8121 allows for external adjustment of
the channel-to-channel current balancing (via the R ISEN
resistors), it is desirable to have a symmetrical layout,
preferably with the controller equidistantly located from
the two power trains it controls. Equally important are
the gate drive lines (UG, LG, PHASE): since they drive
the power train MOSFETs using short, high current
pulses, it is important to size them accordingly and
reduce their overall impedance. Equidistant placement of
the controller to the two power trains also helps keeping
21
these traces equally long (equal impedances, resulting in
similar driving of both sets of MOSFETs).
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize
the length of the connections between the input
capacitors, C IN , and the power switches. Locate the
output inductors and output capacitors between the
MOSFETs and the load. Locate all the high-frequency
decoupling capacitors (ceramic) as close as practicable to
their decoupling target, making use of the shortest
connection paths to any internal planes, such as vias to
GND immediately next, or even onto the capacitor’s
grounded solder pad.
The critical small components include the bypass
capacitors for VCC and PVCC. Locate the bypass
capacitors, C BP , close to the device. It is especially
important to locate the components associated with the
feedback circuit close to their respective controller pins,
since they belong to a high-impedance circuit loop,
sensitive to EMI pick-up. It is important to place the
R ISEN resistors close to the respective terminals of the
ISL8121.
A multi-layer printed circuit board is recommended.
Figure 26 shows the connections of the critical
components for one output channel of the converter.
Note that capacitors C xxIN and C xxOUT could each
represent numerous physical capacitors. Dedicate one
solid layer, usually the one underneath the component
side of the board, for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
Keep the metal runs from the PHASE terminal to inductor
L OUT short. The power plane should support the input
power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the
phase nodes. Use the remaining printed circuit layers for
small signal wiring.
Size the trace interconnects commensurate with the
signals they are carrying. Use narrow (0.005” to
0.008”) and short traces for the high-impedance, small-
signal connections, such as the feedback,
compensation, soft-start, frequency set, enable,
reference track, etc. The wiring traces from the IC to
the MOSFETs’ gates and sources should be wide (0.02”
to 0.05”) and short, encircling the smallest area
possible.
FN6352.2
October 27, 2009
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ISL8126CRZ 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC(0.154",3.90mm 宽) 包装:带卷 (TR)
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