参数资料
| 型号： | ISL8121IRZ |
| 厂商： | Intersil |
| 文件页数： | 23/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 66% |
| 电源电压： | 4.9 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
ISL8121
P UMOS , 2 ≈ V IN ? ------------- – ------------- ? ? ---- 2 ? f S
LOWER MOSFET POWER CALCULATION
Since virtually all of the heat loss in the lower MOSFET is
conduction loss (due to current conducted through the
channel resistance, r DS(ON) ), a quick approximation for
heat dissipated in the lower MOSFET can be found in
Equation 25:
over a time t 2 , and the approximate the power loss is
P UMOS,2 .
? I OUT I L , PP ? ? t ? (EQ. 28)
? N 2 ? ? 2 ?
A third component involves the lower MOSFET’s reverse-
I L , PP ( 1 – D )
? I OUT ? 2
? 2 ?
P LMOS1 = r DS ( ON )
2
? ------------- ? ( 1 – D ) + --------------------------------
12
(EQ. 25)
recovery charge, Q RR . Since the lower MOSFET’s body
diode conducts the full inductor current before it has fully
switched to the upper MOSFET, the upper MOSFET has to
where: I M is the maximum continuous output current,
I L,PP is the peak-to-peak inductor current, and D is the
duty cycle (approximately V OUT /V IN ).
provide the charge required to turn off the lower
MOSFET’s body diode. This charge is conducted through
the upper MOSFET across VIN, the power dissipated as a
result, P UMOS,3 can be approximated as:
An additional term can be added to the lower-MOSFET
loss equation to account for additional loss accrued
P UMOS , 3 = V IN Q rr f S
(EQ. 29)
I PP2
(EQ. 30)
? I OUT ?
P UMOS , 4 = r DS ( ON ) ? ------------- ? d + ----------
during the dead time when inductor current is flowing
through the lower-MOSFET body diode. This term is
dependent on the diode forward voltage at I M , V D(ON) ;
the switching frequency, f S ; and the length of dead
times, t d1 and t d2 , at the beginning and the end of the
lower-MOSFET conduction interval, respectively.
Lastly, the conduction loss part of the upper MOSFET’s
power dissipation, P UMOS,4, can be calculated using
Equation 30:
2
? N ? 12
? I OUT I PP ?
P LMOS 2 = V D ( ON ) f S ? ------------- + --------- ? t
? I OUT I PP ?
+ ? ------------- – --------- ? t d2
? 2 2 ? d1
? 2 2 ?
(EQ. 26)
In this case, of course, r DS(ON) is the ON-resistance of
the upper MOSFET.
The total power dissipated by the upper MOSFET at full
P UMOS , 1 ≈ V IN ? ------------- + ------------- ? ? ---- 1 ? f S
Equation 26 assumes the current through the lower
MOSFET is always positive; if so, the total power
dissipated in each lower MOSFET is approximated by the
summation of P LMOS1 and P LMOS2 .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the
upper-MOSFET losses are switching losses, due to
currents conducted through the device while the input
voltage is present as V DS . Upper MOSFET losses can be
divided into separate components, separating the
upper-MOSFET switching losses, the lower-MOSFET body
diode reverse recovery charge loss, and the upper
MOSFET r DS(ON) conduction loss.
In most typical circuits, when the upper MOSFET turns
off, it continues to conduct a decreasing fraction of the
output inductor current as the voltage at the phase node
falls below ground. Once the lower MOSFET begins
conducting (via its body diode or enhancement channel),
the current in the upper MOSFET decreases to zero. In
Equation 27, the required time for this commutation is
t 1 and the associated power loss is P UMOS,1 .
? I OUT I L , PP ? ? t ? (EQ. 27)
? N 2 ? ? 2 ?
Similarly, the upper MOSFET begins conducting as soon
as it begins turning on. Assuming the inductor current is
in the positive domain, the upper MOSFET sees
approximately the input voltage applied across its drain
and source terminals, while it turns on and starts
conducting the inductor current. This transition occurs
23
load can be approximated as the summation of these
results. Since the power equations depend on MOSFET
parameters, choosing the correct MOSFETs can be an
iterative process that involves repetitively solving the
loss equations for different MOSFETs and different
switching frequencies until converging upon the best
solution.
OUTPUT CAPACITOR SELECTION
The output capacitor is selected to meet both the
dynamic load requirements and the voltage ripple
requirements. The load transient a microprocessor
impresses is characterized by high slew rate (di/dt)
current demands. In general, multiple high quality
capacitors of different size and dielectric are paralleled to
meet the design constraints.
Should the load be characterized by high slew rates,
attention should be particularly paid to the selection and
placement of high-frequency decoupling capacitors
(MLCCs, typically multi-layer ceramic capacitors). High
frequency capacitors supply the initially transient
current and slow the load rate-of-change seen by the
bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and capacitance requirements.
High frequency decoupling capacitors should be placed
as close to the power pins of the load, or for that reason,
to any decoupling target they are meant for, as physically
possible. Attention should be paid as not to add
inductance in the circuit board wiring that could cancel
the usefulness of these low inductance components.
FN6352.2
October 27, 2009
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| ISL8121IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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