参数资料
| 型号： | ISL8121IRZ |
| 厂商： | Intersil |
| 文件页数： | 19/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 66% |
| 电源电压： | 4.9 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
ISL8121
C2
1. Select a value for R1 (1k Ω to 5k Ω , typically).
Calculate value for R2 for desired converter
bandwidth (F 0 ). If setting the output voltage via an
offset resistor connected to the FB pin, Ro in
COMP
R2
C1
R3
C3
Figure 24, the design procedure can be followed as
presented. However, when setting the output
voltage via a resistor divider placed at the input of
-
the differential amplifier, in order to compensate for
E/A
+
FB
Ro
R1
the attenuation introduced by the resistor divider,
the obtained R2 value needs be multiplied by a
VREF
factor of (R P +R S )/R P . The remainder of the
calculations remain unchanged, as long as the
V OSC ? R1 ? F 0
d MAX ? V IN ? F LC
-
VDIFF
VSEN-
compensated R2 value is used.
R2 = ---------------------------------------------
(EQ. 15)
PWM
CIRCUIT
+
OSCILLATOR
V OSC
VSEN+
V IN
V OUT
2. Calculate C1 such that F Z1 is placed at a fraction of the
F LC , at 0.1 to 0.75 of F LC (to adjust, change the 0.5
factor to desired number). The higher the quality
factor of the output filter and/or the higher the ratio
F CE /F LC , the lower the F Z1 frequency (to maximize
phase boost at F LC ).
C1 = ------------------------------------------------
C2 = ---------------------------------------------------------
HALF-BRIDGE
DRIVE
UG
PHASE
LG
L
D
C
E
1
2 π ? R2 ? 0.5 ? F LC
3. Calculate C2 such that F P1 is placed at F CE .
C1
2 π ? R2 ? C1 ? F CE – 1
(EQ. 16)
(EQ. 17)
(EQ. 14)
F LC = ---------------------------
F CE = ------------------------
1
R3 = ----------------------
F SW
2 π ? R3 ? 0.7 ? F SW
G MOD ( f ) = ------------------------------ ? ----------------------------------------------------------------------------------------
V OSC
1 + s ( f ) ? ( E + D ) ? C + s ( f ) ? L ? C
G FB ( f ) = ------------------------------------------------------ ?
s ( f ) ? R1 ? ( C1 + C2 )
? -----------------------------------------------------------------------------------------------------------------------------
( 1 + s ( f ) ? R3 ? C3 ) ? ? 1 + s ( f ) ? R2 ? ? ---------------------- ? ?
ISL8121 EXTERNAL CIRCUIT
FIGURE 24. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal
transfer function of V OUT /V COMP . This function is
dominated by a DC gain, given by d MAX V IN /V OSC , and
shaped by the output filter, with a double pole break
frequency at F LC and a zero at F CE . For the purpose of
this analysis, L and D represent the individual channel
inductance and its DCR divided by 2 (equivalent parallel
value of the two output inductors), while C and E
represents the total output capacitance and its
equivalent series resistance.
1 1
2 π ? L ? C 2 π ? C ? E
The compensation network consists of the error amplifier
(internal to the ISL8121) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB
crossing frequency (F 0 ; typically 0.1 to 0.3 of F SW ) and
adequate phase margin (better than 45 degrees). Phase
margin is the difference between the closed loop phase
at F 0dB and 180°. The equations that follow relate the
compensation network’s poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 23.
4. Calculate R3 such that F Z2 is placed at F LC . Calculate
C3 such that F P2 is placed below F SW (typically, 0.5
to 1.0 times F SW ). F SW represents the per-channel
switching frequency. Change the numerical factor to
reflect desired placement of this pole. Placement of
F P2 lower in frequency helps reduce the gain of the
compensation network at high frequency, in turn
reducing the HF ripple component at the COMP pin
and minimizing resultant duty cycle jitter.
R1
C3 = ------------------------------------------------- (EQ. 18)
------------ – 1
F LC
It is recommended a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results
and adjust as necessary. Equation 19 describes the
frequency response of the modulator (G MOD ), feedback
compensation (G FB ) and closed-loop response (G CL ):
d MAX ? V IN 1 + s ( f ) ? E ? C
2
1 + s ( f ) ? R2 ? C1
(EQ. 19)
1 + s ( f ) ? ( R1 + R3 ) ? C3
C1 ? C2
? ? C1 + C2 ? ?
Use the following guidelines for locating the poles and
zeros of the compensation network:
19
G CL ( f ) = G MOD ( f ) ? G FB ( f )
where , s ( f ) = 2 π ? f ? j
FN6352.2
October 27, 2009
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| ISL8121IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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| ISL8126CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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