参数资料
型号: ISL8121IRZ
厂商: Intersil
文件页数: 7/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 24-QFN
标准包装: 75
PWM 型: 电压模式
输出数: 1
频率 - 最大: 2MHz
占空比: 66%
电源电压: 4.9 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-VFQFN 裸露焊盘
包装: 管件
ISL8121
Functional Pin Descriptions
VCC (Pin 8)
Bias supply for the IC’s small-signal circuitry. Connect
this pin to a 5V supply and locally decouple using a
quality 0.1μF ceramic capacitor. This pin is monitored for
POR purposes. VCC bias may be applied in the absence
of PVCC bias.
PVCC (Pin 15)
Power supply pin for the MOSFET drives. Connect this pin
to a 5V supply and locally decouple using a quality 1μF
ceramic capacitor. This pin is monitored for POR
purposes. PVCC bias should not be applied in the
absence of VCC bias.
VREG (Pin 7)
This pin is the output of the internal shunt regulator. The
internal shunt regulator monitors and regulates the
voltage at the VCC pin. In applications where the chip
bias, including that necessary to drive the external
MOSFETs, is below the current rating of this pin, connect
it to VCC and PVCC, then connect this node to the input
supply via a properly sized resistor. Should the input
voltage vary over a wide range and/or the bias current
required exceed the intrinsic capability of the on-board
regulator, use this pin in conjunction with an external
NPN transistor and a couple of resistors to create a more
flexible bias supply for the ISL8121. In any configuration,
pay particular attention to the chip’s limitations in terms
of both current sinking capability of the shunt regulator,
as well as the internal power dissipation.
For more information, see “Bias Supply Considerations”
GND (Pin 25)
Connect this pad to the circuit ground using the shortest
possible path (one to four vias to the internal ground
plane, placed on the soldering pad are recommended).
All internal small-signal circuitry, as well as the lower
gates’ return paths are referenced to this pin.
REFTRK (Pin 24)
This pin represents an optional reference input, as well
as a clamp voltage for the internal reference. If utilizing
the ISL8121’s internal 0.6V reference, and desire no
special tracking features enabled, electrically connect
this pin to the VCC pin, or leave it open. Internal or
external reference operation mode is dictated by the
VMON pin.
While operating in internal reference mode, this pin
represents an internal reference clamp that can be used
for implementation of various tracking features. In this
operating mode, a small internal current is sourced on
this pin, pulling it high if left open.
If utilizing the ISL8121 in conjunction with an external
reference, connect the desired stimulus to this pin; the
sensed output of the ISL8121 converter follows this
input.
7
While operating with an external reference, the power-
good and overvoltage protection functions are disabled
while the VMON pin voltage is below its threshold
(typically 300mV).
VMON (Pin 3)
The status of this pin is checked every time the chip is
enabled or POR is released; should its potential be lower
than 3.5V (typical), the REFTRK potential is assumed to
be an externally-provided reference and the ISL8121
proceeds to regulate the sensed output voltage to this
external reference. When operating using the internal
reference voltage, connect this pin to VCC (to bypass
the mechanism described above).
While operating with an externally-provided reference,
connect this pin to a properly-sized resistor divider off
the voltage to be monitored. PGD and OVP functions are
enabled when this pin exceeds its monitored threshold
(typically 300mV).
This pin is normally floating (high impedance input) until
it exceeds its detect threshold. Once the threshold is
exceeded, a small current is sourced on this pin; this
current, along with a properly sized resistor network,
allows the user to adjust the threshold hysteresis.
For more information, refer to “External Reference
EN (Pin 9)
This pin is a precision-threshold (approximately 0.6V)
enable pin. Pulled above the threshold, the pin enables
the controller for operation, initiating a soft-start.
Normally a high impedance input, once it is pulled
above its threshold, a small current is sourced on this
pin; this current, along with a properly sized resistor
network, allows the user to adjust the threshold
hysteresis. Pulled below the falling threshold, this pin
disables controller operation, by ramping down the SS
voltage and discharging the output.
VSEN+, VSEN-, and VDIFF (Pins 2, 1, and 4)
The inputs and output of the on-board unity-gain
operational amplifier intended for differential output
sensing. Connect VSEN- and VSEN+ to the output load’s
local GND and VOUT, respectively; VDIFF will reflect the
load voltage referenced to the chip’s local ground.
Connect the feedback network to the voltage thus
reflected at the VDIFF pin. Should the circuit not allow
implementation of remote sensing, connect the VSEN+
and VSEN- pins to the physical place where voltage is to
be regulated.
Connect the resistor divider setting the output voltage at
the input of the differential amplifier. To minimize the
error introduced by the resistance of differential
amplifier’s inputs, select resistor divider values smaller
than 1k Ω . VDIFF is monitored for overvoltage events and
for PGD reporting purposes.
FN6352.2
October 27, 2009
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