参数资料
| 型号： | ISL8121IRZ |
| 厂商： | Intersil |
| 文件页数： | 8/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 66% |
| 电源电压： | 4.9 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
ISL8121
FB and COMP (Pins 5 and 6)
The internal error amplifier’s inverting input and output
respectively. These pins are connected to the external
network used to compensate the regulator’s feedback
loop.
ISEN1, ISEN2 (Pins 17, 13)
These pins are used to close the current feedback loop
and set the overcurrent protection threshold. A resistor
connected between each of these pins and their
corresponding PHASE pins determine a certain current
flow magnitude during the lower MOSFET’s conduction
interval. The resulting currents established through these
resistors are used for channel current balancing and
overcurrent protection.
Use Equation 1 to select the proper R ISEN resistor:
during start-up. Connect this pin to a capacitor
referenced to ground. Small internal current sources
linearly charge and discharge this capacitor, leading to
similar variation in the ramp up/down of the output
voltage. While below 0.3V, all output drives are turned
off. As this pin ramps up, the drives are not enabled but
only after the first UG pulse emerges (avoid draining the
output, if pre-charged). If no UG pulse are generated
until the SS exceeds the top of the oscillator ramp, at
that time all gate operation is enabled, allowing
immediate draining of the output, as necessary.
SS voltage has a ~0.7V offset above the reference
clamp, meaning the reference clamp rises from 0V with
unity gain correspondence as the SS pin exceeds 0.7V.
For more information, please refer to “Soft-Start” on
R ISEN = ------------------------------------------
r DS ( ON ) × I OUT
50 μ A
(EQ. 1)
FS (Pin 22)
This pin is used to set the switching frequency. Connect
where:
r DS(ON) = lower MOSFET drain-source ON resistance ( Ω )
I OUT = channel maximum output current (A)
information.
UG1, UG2 (Pins 19, 11)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes.
Minimize the impedance of these connections. Maximum
individual channel duty cycle is limited to 66%.
BOOT1, BOOT2 (Pins 20, 10)
These pins provide the bias voltage for the upper
MOSFETs’ drives. Connect these pins to appropriately-
chosen external bootstrap capacitors. Internal bootstrap
a resistor, R FS , from this pin to ground and size it
according to the graph in Figure 1 or Equation 2.
( 10.61 – ( 1.035 ? log ( F SW ) ) ) (EQ. 2)
R FS = 10
200k
100k
50k
20k
diodes connected to the PVCC pins provide the necessary
bootstrap charge. Minimize the impedance of these
10k
100k
200k
500k
1M
2M
connections.
PHASE1, PHASE2 (Pins 18, 12)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’
drives. Minimize the impedance of these connections.
LG1, LG2 (Pins 16, 14)
These pins are used to control the lower MOSFETs and
are monitored for shoot-through prevention purposes.
Connect these pins to the lower MOSFETs’ gates.
Minimize the impedance of these connections.
SS (Pin 23)
This pin allows adjustment of the output voltage
soft-start ramp rate, as well as the hiccup interval
following an overcurrent event. The potential at this pin
is used as a clamp voltage for the internal error
amplifier’s non-inverting input, regulating its rate of rise
8
SWITCHING FREQUENCY (Hz)
FIGURE 1. SWITCHING FREQUENCY VS. R FS VALUE
PGD (Pin 21)
This pin represents the output of the on-board
power-good monitor. Thus, the FB pin is monitored and
compared against a window centered around the
available reference; an FB voltage within the window
disables the open-collector output, allowing the external
resistor to pull-up PGD high. Approximate pull-down
device impedance is 65 Ω .
While operating with an external reference, the
power-good function is enabled once the VMON pin
amplitude exceeds its monitored threshold (typically
300mV).
FN6352.2
October 27, 2009
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相关代理商/技术参数 |
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| ISL8121IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8121IRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL8121IRZ-T WITH GOLD BOND WIRE ONLY - Tape and Reel |
| ISL8126 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual/n-Phase Buck PWM Controller with Integrated Drivers |
| ISL8126CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8126CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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