参数资料
| 型号： | ISL8121IRZ |
| 厂商： | Intersil |
| 文件页数： | 20/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 24-QFN |
| 标准包装： | 75 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 66% |
| 电源电压： | 4.9 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 包装： | 管件 |
ISL8121
COMPENSATION BREAK FREQUENCY EQUATIONS
system transient response leaving the output capacitor
F Z1 = --------------------------------
F P1 = -----------------------------------------------
2 π ? R2 ? ----------------------
F Z2 = ---------------------------------------------------
F P2 = --------------------------------
1
2 π ? R2 ? C1
1
2 π ? ( R1 + R3 ) ? C3
1
C1 ? C2
C1 + C2
1
2 π ? R3 ? C3
(EQ. 20)
bank to supply the load current or sink the inductor
currents, all while the current in the output inductors
increases or decreases to meet the load demand.
In high-speed converters, the output capacitor bank is
amongst the costlier (and often the physically largest)
Figure 25 shows an asymptotic plot of the DC/DC
converter’s gain vs frequency. The actual Modulator Gain
has a high gain peak dependent on the quality factor (Q)
of the output filter, which is not shown. Using the
previously mentioned guidelines should yield a
compensation gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F P2 against the
capabilities of the error amplifier. The closed loop gain,
G CL , is constructed on the log-log graph of Figure 25 by
adding the modulator gain, G MOD (in dB), to the
feedback compensation gain, G FB (in dB). This is
equivalent to multiplying the modulator transfer function
and the compensation transfer function and then plotting
the resulting gain.
parts of the circuit. Output filter design begins with
consideration of the critical load parameters: maximum
size of the load step, Δ I, the load-current slew rate, di/dt,
and the maximum allowable output voltage deviation
under transient loading, Δ V MAX . Capacitors are
characterized according to their capacitance, ESR, and
ESL (equivalent series inductance).
At the beginning of the load transient, the output
capacitors supply all of the transient current. The output
voltage will initially deviate by an amount approximated
by the voltage drop across the ESL. As the load current
increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value. The
capacitors selected must have sufficiently low ESL and
ESR so that the total output-voltage deviation is less
F Z1 F Z2
F P1
F P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
than the allowable maximum. Neglecting the contribution
of inductor current and regulator response, the output
voltage initially deviates according to Equation 21:
Δ V ≈ ( ESL ) ----- + ( ESR ) Δ I
di
dt
(EQ. 21)
The filter capacitor must have sufficiently low ESL and
20 log ? -------- ?
0
R2
? R1 ?
d MAX ? V IN
20 log ---------------------------------
V OSC
G CL
G FB
ESR so that Δ V < Δ V MAX .
Most capacitor solutions rely on a mixture of high-
frequency capacitors with relatively low capacitance in
combination with bulk capacitors having high capacitance
but limited high-frequency performance. Minimizing the
G MOD
ESL of the high-frequency capacitors allows them to
support the output voltage as the current increases.
LOG
F LC
F CE
F 0
FREQUENCY
Minimizing the ESR of the bulk capacitors allows them to
supply the increased current with less output voltage
( V IN – 2 ? V OUT ) ? V OUT
f S ? V IN ? V PP ( MAX )
FIGURE 25. ASYMPTOTIC BODE PLOT OF CONVERTER
GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than
45°. Include worst case component variations when
determining phase margin. The mathematical model
presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover
frequencies in the range of 10% to 30% of the per-
channel switching frequency, F SW .
OUTPUT FILTER DESIGN
The output inductors and the output capacitor bank
together form a low-pass filter responsible for smoothing
the square wave voltage at the phase nodes.
Additionally, the output capacitors must also provide the
energy required by a fast transient load during the short
interval of time required by the controller and power train
to respond. Because it has a low bandwidth compared to
the switching frequency, the output filter limits the
20
deviation.
The ESR of the bulk capacitors is also responsible for the
majority of the output-voltage ripple. As the bulk
capacitors sink and source the inductor AC ripple current,
a voltage develops across the bulk-capacitor ESR equal
to I PP . Thus, once the output capacitors are selected and
a maximum allowable ripple voltage, V PP(MAX) , is
determined from an analysis of the available output
voltage budget, Equation 22 can be used to determine a
lower limit on the output inductance.
L ≥ ESR ? ----------------------------------------------------------------- (EQ. 22)
Since the capacitors are supplying a decreasing portion
of the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly
depleted. The output inductors must be capable of
assuming the entire load current before the output
voltage decreases more than Δ V MAX . This places an
upper limit on inductance.
FN6352.2
October 27, 2009
相关PDF资料 |
PDF描述 |
|---|---|
| ISL8126IRZ | IC REG CTRLR BUCK PWM VM 32-QFN |
| ISL8130IAZ | IC REG CTRLR BST FLYBK VM 20QSOP |
| ISL85001IRZ-T | IC REG BUCK ADJ 1A 12DFN |
| ISL8500IRZ-T | IC REG BUCK ADJ 2A 12DFN |
| ISL8502AIRZ | IC REG BUCK SYNC ADJ 2A 24QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL8121IRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 24-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8121IRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL8121IRZ-T WITH GOLD BOND WIRE ONLY - Tape and Reel |
| ISL8126 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Dual/n-Phase Buck PWM Controller with Integrated Drivers |
| ISL8126CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL8126CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。