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参数资料
| 型号： | LTC3876EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DC/DC DDR DUAL 38-TSSOP |
| 产品培训模块： | LTC3876 Dual DC/DC Controller |
| 标准包装： | 50 |
| 应用： | 控制器，DDR，DDR2，DDR3 |
| 输入电压： | 4.5 V ~ 38 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 管件 |
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LTC3876
OPERATION
(Refer to Functional Diagram)
and INTV CC with the external voltage source and helping
to increase overall efficiency and decrease internal self
heating from power dissipated in the LDO. This exter-
nal power source could be the output of the step-down
converter itself, given that the output is programmed to
higher than 4.7V. The V IN pin still needs to be powered up
but now draws minimum current.
Power for most internal control circuitry other than gate
drivers is derived from the INTV CC pin. INTV CC can be pow-
ered from the combined DRV CC pins through an external
RC filter to SGND to filter out noises due to switching.
Shutdown and Start-Up
The RUN pin has an internal proportional-to-absolute
temperature (PTAT) current source (around 2.5μA at 25°C)
to pull up the pin. Taking the RUN pin below a certain
threshold voltage (around 0.8V at 25°C) shuts down all
bias of INTV CC and DRV CC and places the LTC3876 into
micropower shutdown mode with a minimum I Q at the
V IN pin. The LTC3876’s DRV CC (through the internal 5.3V
LDO regulator or EXTV CC ) and the corresponding channel’s
internal circuitry off INTV CC will be biased up when either
or both RUN pins are pulled up above the 0.8V threshold,
either by the internal pull-up current or driven directly by
external voltage source such as logic gate output.
No channel of the LTC3876 will start switching until
the RUN pin is pulled up to 1.2V. When the RUN pin
rises above 1.2V, the TG and BG drivers are enabled, and
TRACK/SS released. An additional 10μA temperature-
independent pull-up current is connected internally
to the RUN pin. To turn off TG, BG and the additional
10μA pull-up current, RUN needs to be pulled down
below 1.2V by about 100mV. These built-in current and
voltage hystereses prevent false jittery turn-on and turn-off
due to noise. Such features on the RUN pin allows input
undervoltage lockout (UVLO) to be set up using external
voltage dividers from V IN .
At start-up channel 1 is controlled by the voltage on the
TRACK/SS pin and channel 2 tracks 0.500 ? (VDDQSNS
– V OUTSENSE1– ). When the voltage on the TRACK/SS pin
is less than the 0.6V internal reference, the (differential)
feedback voltage is regulated to the TRACK/SS voltage
used to program the output voltage soft-start ramp-up time
by connecting an external capacitor from a TRACK/SS pin
to signal ground. An internal temperature-independent 1μA
pull-up current charges this capacitor, creating a voltage
ramp on the TRACK/SS pin. As the TRACK/SS voltage rises
linearly from ground to 0.6V, the switching starts, VDDQ
ramps up smoothly to its final value and the feedback
voltage to 0.6V. TRACK/SS will keep rising beyond 0.6V,
until being clamped to around 3.7V.
Alternatively, the TRACK/SS pin can be used to track an
external supply like in a master slave configuration. Typi-
cally, this requires connecting a resistor divider from the
master supply to the TRACK/SS pin (see the Applications
Information section).
TRACK/SS1 is pulled low internally when the correspond-
ing channel’s RUN pin is pulled below the 1.2V threshold
(hysteresis applies), or when INTV CC or either of the
DRV CC1,2 pins drop below their respective undervoltage
lockout (UVLO) thresholds.
Channel 1 VDDQ Light Load Operation
If the MODE/PLLIN pin is tied to INTV CC or an external clock
is applied to MODE/PLLIN, the LTC3876 will be forced to
operate in continuous mode. With load current less than
one-half of the full load peak-to-peak ripple, the inductor
current valley can drop to zero or become negative. This
allows constant-frequency operation but at the cost of low
efficiency at light loads.
If the MODE/PLLIN pin is left open or connected to signal
ground, channel 1 will transition into discontinuous mode
operation, where a current reversal comparator (I REV )
shuts off the bottom MOSFET (M B ) as the inductor cur-
rent approaches zero, thus preventing negative inductor
current and improving light-load efficiency. Only VDDQ
channel 1 is allowed to operate in discontinuous mode.
The VTT channel 2 operates in forced continuous mode at
all times independent of the MODE/PLLIN setting. In this
mode, both channel 1 switches remain off. As the output
capacitor discharges by load current and the output volt-
age droops lower, channel 1 EA will eventually move the
ITH voltage above the zero current level (0.8V) to initiate
another switching cycle.
instead of the 0.6V reference. The TRACK/SS pin can be
3876f
16
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