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参数资料
| 型号： | LTC3876EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DC/DC DDR DUAL 38-TSSOP |
| 产品培训模块： | LTC3876 Dual DC/DC Controller |
| 标准包装： | 50 |
| 应用： | 控制器，DDR，DDR2，DDR3 |
| 输入电压： | 4.5 V ~ 38 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 管件 |
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LTC3876
OPERATION
(Refer to Functional Diagram)
Power Good and Fault Protection
The PGOOD pin is connected to an internal open-drain
N-channel MOSFET. An external resistor or current source
can be used to pull this pin up to 6V (e.g., VDDQ/VTT or
DRV CC ). Overvoltage or undervoltage comparators (OV, UV)
turn on the MOSFET and pull the PGOOD pin low when the
feedback voltage is outside the ±7.5% window of the 0.6V
reference voltage. The PGOOD pin is also pulled low when the
channel’s RUN pin is below the 1.2V threshold (hysteresis
applies), or in undervoltage lockout (UVLO). Note that feed-
back voltage of channel 1 is sensed differentially through
V OUTSENSE1+ with respect to V OUTSENSE1– , while channel 2
is sensed through VTTSNS. PGOOD is only high when both
channels are within window.
When the feedback voltage of channel 1 is within the
±7.5% window and channel 2 within the ±10% window,
the open-drain NMOS is turned off and the pin is pulled
up by the external source. The PGOOD pin will indicate
power good immediately after the feedback is within the
window. But when a feedback voltage of a channel goes
out of the window, there is an internal 50μs delay before
its PGOOD is pulled low. In an overvoltage (OV) condition,
M T is turned off and M B is turned on immediately without
delay and held on until the overvoltage condition clears.
Foldback current limiting is provided if the output is below
one-half of the regulated voltage, such as being shorted to
ground. As the feedback drops below one-half of the normal
regulation point approaching 0V, the internal ITH clamp
voltage gradually drops 2.4V to 1.3V for VDDQ channel 1
and 2.2V to 1.8V for VTT channel 2. This reduces the induc-
tor valley current level to about one-third of its maximum
value as the feedback approaches 0V. Foldback current
limiting is disabled at start-up.
ing the top MOSFET turn-on time (on-time) through the
one-shot timer. This is achieved by sensing the phase
relationship between a top MOSFET turn-on signal and
its internal reference clock through a phase detector. The
time interval of the one-shot timer is adjusted on a cycle-
by-cycle basis, so that the rising edge of the top MOSFET
turn-on is always trying to synchronize to the internal
reference clock signal for the respective channel.
The frequency of the internal oscillator can be programmed
from 200kHz to 2MHz by connecting a resistor, R T , from the
RT pin to signal ground (SGND). The RT pin is regulated
to 1.2V internally.
For applications with stringent frequency or interference
requirements, an external clock source connected to the
MODE/PLLIN pin can be used to synchronize the internal
clock signals through a clock phase-locked loop (Clock
PLL). The LTC3876 operates in forced continuous mode
of operation when it is synchronized to the external clock.
The external clock frequency has to be within ±30% of the
internal oscillator frequency for successful synchroniza-
tion. The clock input levels should be no less than 2V for
“high” and no greater than 0.5V for “low”. The MODE/
PLLIN pin has an internal 600k pull-down resistor.
Multichip Operations
The PHASMD pin determines the relative phases between
the internal reference clock signals for the two channels
as well as the CLKOUT signal, as shown in Table 1. The
phases tabulated are relative to zero degree (0°) being
defined as the rising edge of the internal reference clock
signal of channel 1. The CLKOUT signal can be used to
synchronize additional power stages in a multiphase power
supply solution feeding either a single high current output,
or separate outputs.
Frequency Selection and External Clock
Synchronization
An internal oscillator (clock generator) provides phase-
interleaved internal clock signals for individual channels
to lock up to. The switching frequency and phase of each
Table 1
PHASMD
VDDQ Channel 1
VTT Channel 2
CLKOUT
SGND
0°
180°
60°
FLOAT
0°
180°
90°
INTV CC
0°
240°
120°
switching channel is independently controlled by adjust-
3876f
17
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