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| 型号： | LTC3876EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DC/DC DDR DUAL 38-TSSOP |
| 产品培训模块： | LTC3876 Dual DC/DC Controller |
| 标准包装： | 50 |
| 应用： | 控制器，DDR，DDR2，DDR3 |
| 输入电压： | 4.5 V ~ 38 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 管件 |
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LTC3876
APPLICATIONS INFORMATION
Once the required output voltage and operating frequency
have been determined, external component selection is
driven by load requirement, and begins with the selec-
tion of inductors and current sense method (either sense
resistors R SENSE or inductor DCR sensing). Next, power
MOSFETs are selected. Finally, input and output capaci-
tors are selected.
Output Voltage Programming
As shown in Figure 1, external resistor dividers are used
from the regulated outputs to their respective ground
references to program the output voltages. On channel 1,
the resistive divider is tapped by the V OUTSENSE1+ pin,
and the ground reference is remotely sensed by the
V OUTSENSE1– pin, this voltage is sensed differentially.
Connect the VTTSNS pin directly to the VTT output. By
regulating the tapped (differential) feedback voltages to the
internal reference 0.6V, the resulting output voltages are:
V(VDDQ) – V OUTSENSE1– = 0.6V ? (1 + R FB2 /R FB1 )
and
V(VTT) = 0.500 ? (VDDQ – V OUTSENSE1– )
For example, if V OUT1 is programmed to 1.5V and the
output ground reference is sitting at –0.5V with respect to
SGND, then the absolute value of the output will be 2.0V
with respect to SGND. The minimum (differential) output
voltages are limited to the internal reference 0.6V, and the
maximum are 5.5V.
The V OUTSENSE1+ pin is a high impedance pin with no
input bias current other than leakage in the nA range. The
V OUTSENSE1– pin has about 30μA of current flowing out
of the pin. The VTTSNS pin is quasi-high impedance pin
with minimum bias current out of the pin.
Differential output sensing allows for more accurate output
regulation in high power distributed systems having large
line losses. Figure 2 illustrates the potential variations in
the power and ground lines due to parasitic elements.
The variations may be exacerbated in multi-application
systems with shared ground planes. Without differential
output sensing, these variations directly reflect as an error
in the regulated output voltage. The LTC3876 channel 1’s
differential output sensing can correct for up to ±500mV
of variation in the output’s power and ground lines.
The LTC3876 channel 1’s differential output sensing scheme
is distinct from conventional schemes where the regulated
output and its ground reference are directly sensed with
a difference amplifier whose output is then divided down
with an external resistor divider and fed into the error
amplifier input. This conventional scheme is limited by
the common mode input range of the difference amplifier
and typically limits differential sensing to the lower range
of output voltages.
The LTC3876’s channel 1 allows for seamless differential
output sensing by sensing the resistively divided feedback
voltage differentially. This allows for differential sensing in
the full output range. The difference amplifier (DIFFAMP)
of the LTC3876 has a bandwidth of 8MHz, high enough
so that it will not affect main loop compensation and
transient behavior.
LTC3876
V OUTSENSE1+
C FF
(OPT)
R FB2
V OUT
C OUT
To avoid noise coupling into the feedback voltage
(V OUTSENSE1+ ), the resistor dividers should be placed close
to the V OUTSENSE1+ and V OUTSENSE1– . Remote output and
ground traces should be routed together as a differential
R FB1
pair to the remote output. For best accuracy, these traces
V OUTSENSE1–
3876 F01
to the remote output and ground should be connected as
close as possible to the desired regulation point.
Figure 1. Setting Output Voltage
3876f
18
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