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| 型号： | LTC3876EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 25/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DC/DC DDR DUAL 38-TSSOP |
| 产品培训模块： | LTC3876 Dual DC/DC Controller |
| 标准包装： | 50 |
| 应用： | 控制器，DDR，DDR2，DDR3 |
| 输入电压： | 4.5 V ~ 38 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 管件 |
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LTC3876
APPLICATIONS INFORMATION
the capacitors. A lower input inductance will result in less
ripple current through the input capacitors since more
ripple current will now be flowing out of the input source.
For simulating positive output current loading using this
model, look at the ripple current during steady-state for
the case where one phase is fully loaded and the other
is not loaded. This will in general be the worst-case for
ripple current since the ripple current from one phase will
not be cancelled by ripple current from the other phase.
The LTC3876 is more complex than this example because
the VTT channel can provide significant negative current.
For the LTC3876 steady state worst-case, look at the
condition where VDDQ channel is fully loaded and the
VTT channel is supplying maximum negative current.
This will in general be the worst-case for ripple current
since the ripple current from VTT will add with ripple cur-
rent from VDDQ when the VTT channel sinks or provides
negative current.
Note that the bulk capacitor also has to be chosen for
RMS rating with ample margin beyond its RMS current
per simulation with the circuit model provided. For a lower
operate at sustained negative current for any significant
period of time in normal operation. There could be DDR
test conditions which do exercise such extremes, but again
this should not be continuous. Therefore, determine the
worst-case RMS requirement for the input capacitors and
reduce as appropriate for sufficient margin.
The V IN sources of the top MOSFETs should be placed
close to each other and share common C IN (s). Separating
the sources and C IN may produce undesirable voltage and
current resonances at V IN .
A small (0.1μF to 1μF) bypass capacitor between the IC’s
V IN pin and ground, placed close to the IC, is suggested.
A 2.2Ω to 10Ω resistor placed between C IN and the V IN
pin is also recommended as it provides further isolation
from switching noise of the two channels.
C OUT Selection
The selection of output capacitance C OUT is primarily
determined by the effective series resistance, ESR, to
minimize voltage ripple. The output voltage ripple ? V OUT ,
in continuous mode is determined by:
Δ V OUT ≤ Δ I L ? R ESR +
V IN range, a conductive-polymer type (such as Sanyo
OS-CON) can be used for its higher ripple current rating
and lower ESR. For a wide V IN range that also require
?
?
1 ?
8?f?C OUT ??
higher voltage rating, aluminum-electrolytic capacitors are
more attractive since it can provide a larger capacitance
for more damping. An aluminum-electrolytic capacitor
with a ripple current rating that is high enough to handle
all of the ripple current by itself will be very large. But
when in parallel with ceramics, an aluminum-electrolytic
capacitor will take a much smaller portion of the RMS
ripple current due to its high ESR. However, it is crucial
that the ripple current through the aluminum-electrolytic
capacitor should not exceed its rating since this will
produce significant heat, which will cause the electrolyte
inside the capacitor to dry over time and its capacitance
to go down and ESR to go up.
While it is always safest to choose the input capacitors
RMS rating according to the worst-case single-phase ap-
plication with negative VTT current as discussed above, it is
likely not necessary. For DDR memory, the VTT output load
where f is operating frequency, and ? I L is ripple current
in the inductor. The output ripple is highest at maximum
input voltage since ? I L increases with input voltage. Typi-
cally, once the ESR requirement for C OUT has been met,
the RMS current rating generally far exceeds that required
from ripple current.
In single-output applications, for the same reason that
LTC3876 is only truly phase interleaved at steady state,
ripple current of individual channels could add up in
transient, it is advisable to consider using the worst-case
? I L , i.e., the sum of the ? I L of all individual channels, in
the calculation of ? V OUT .
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage.
current will statistically approach zero and should never
3876f
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