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| 型号： | LTC3876EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 38/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DC/DC DDR DUAL 38-TSSOP |
| 产品培训模块： | LTC3876 Dual DC/DC Controller |
| 标准包装： | 50 |
| 应用： | 控制器，DDR，DDR2，DDR3 |
| 输入电压： | 4.5 V ~ 38 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 管件 |
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LTC3876
APPLICATIONS INFORMATION
The DCR sense filter is designed using a simple RC filter
across the inductor. If the inductor value and DCR is known,
choose a sense filter C and calculate filter resistance.
Channel 1 DCR filter resistor R DCR1 :
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
Select C IN capacitors to give ample capacitance and RMS
R DCR 1 =
L 1
DCR ?C DCR
=
0 . 47 μH
0 . 8 mΩ ? 0 . 1 μF
= 5 . 9 k
ripple current rating. Consider worst-case duty cycles per
Figure 6. If operated at steady-state with SW nodes fully
interleaved, the two channels would generate not more
Channel 2 DCR filter resistor R DCR2 :
than 7.5A RMS at full load. In this design example, 2X
10μF 25V X5R ceramic capacitors are put in parallel to take
R DCR 1 =
L 1
DCR ?C DCR
=
0 . 47 μH
1 . 72 mΩ ? 0 . 1 μF
= 2 . 74 k
the RMS ripple current with 330μF aluminum electrolytic
bulk capacitors for stability. For 10μF 1210 X5R ceramic
capacitors, try to keep the ripple current less than 3A RMS
( 20 A ) 2 ( 1 + 0 . 4% ( 125° C – 25° C ) ) ( 0 . 013 Ω ) +
P TOP =
( 14 V ) 2 ?
? ( 150 pF ) ?
? ( 400 kHz )
? 20 A ? ? 2 . 5 Ω 1 . 2 Ω ?
? 2 ?
? 5 . 3 V – 3 V
3 V ?
14 V – 1 . 5 V ? 20 A ? 2
P BOT = ? ?
The external N-channel MOSFETs are chosen based
on current capability and efficiency. The Renesas
RJK0305DBP(R DS(ON) =13mΩ(maximum),C MILLER =150pF,
VGS = 4.5V, V MILLER = 3V, θ JA = 40°C/W, T J(MAX) = 150°C)
is chosen for the top MOSFET (main switch). The Renesas
RJK0330DBP (R DS(ON) = 3.9mΩ(maximum), V GS = 4.5V,
θ JA = 40°C/W, T J(MAX) =150°C) is chosen for the bottom
MOSFET (synchronous switch).The power dissipation for
each MOSFET can be calculated for V IN = 14V and typical
T J =125°C.
The power dissipation for V IN = 14V and T J =125°C for
the top MOSFET is:
1 . 5 V
14 V
+
= 0 . 78 W + 0 . 17 W = 0 . 95 W
The power dissipation for V IN = 14V and T J =125°C for
2X bottom MOSFETs is:
14 V ? 2 X ?
( 1 + 0 . 4 % ( 125° C – 25° C ) ) ( 0 . 0039 Ω ) = 0 . 4875 W
The resulting junction temperatures for ambient tempera-
through each device. The bulk capacitor is chosen for
RMS rating per simulation with the circuit model provided.
The power supply output capacitor’s C OUT are chosen
for a low ESR. For channel 1 VDDQ, the output capacitor
SANYO 2R5TPE330M9, has an ESR of 9mΩ which results
in 4.5mΩ for two in parallel. For channel 2 VTT, the output
capacitor SANYO 2R5TPE330M9, has an ESR of 9mΩ.
The output ripple for each channel is given as:
ΔVDDQ(RIPPLE) = ΔI L(MAX) (ESR)
= (7.12A) ? (4.5mΩ) = 32mV
ΔVTT(RIPPLE) = ΔI L(MAX) (ESR)
= (3.78A) ? (9mΩ) = 34mV
A 0A to 10A load step in VDDQ will cause an output change
of up to:
ΔVDDQ(STEP) = ΔI LOAD (ESR) = 10A ? 0.0045mΩ =
45mV
A 0A to 5A load step in VTT will cause an output change
of up to:
ΔVTT(STEP) = ΔI LOAD (ESR) = 5A ? 0.009mΩ = 45mV
Optional 100μF ceramic output capacitors are included
to minimize the effect of ESL in the output ripple and to
improve load step response.
ture T A = 75°C are:
T J(TOP) = 75°C + (0.95W)(40°C/W) = 113°C
T J(BOT) = 75°C + (0.975W)(40°C/W) = 94.5°C
3876f
38
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