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| 型号： | LTC3876EFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 32/48页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DC/DC DDR DUAL 38-TSSOP |
| 产品培训模块： | LTC3876 Dual DC/DC Controller |
| 标准包装： | 50 |
| 应用： | 控制器，DDR，DDR2，DDR3 |
| 输入电压： | 4.5 V ~ 38 V |
| 输出数： | 2 |
| 输出电压： | 可调 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 管件 |
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LTC3876
APPLICATIONS INFORMATION
to the minimum on-time of 30ns as shown in Figure 10.
Each of the dead times are in the order of 35ns. Therefore,
the VTT channel minimum on time should be no less than
100ns with 150ns preferred.
In continuous mode operation, the minimum on-time limit
imposes a minimum duty cycle of:
D MIN = f ? t ON(MIN)
where t ON(MIN) is the effective minimum on-time for the
switching regulator. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle
constraint. If the minimum on-time that LTC3876 can
provide is longer than the on-time required by the duty
the other hand, imbalances in turn-on and turn-off delays
could reduce the effective minimum off-time.
The minimum off-time limit imposes a maximum duty
cycle of:
D MAX = 1 – f ? t OFF(MIN)
where t OFF(MIN) is the effective minimum off-time of the
switching regulator. Reducing the operating frequency can
alleviate the maximum duty cycle constraint.
If the maximum duty cycle is reached, due to a drooping
input voltage for example, the output will drop out of
regulation. The minimum input voltage to avoid dropout is:
cycle to maintain the switching frequency, the switching
frequency will have to decrease to maintain the duty cycle,
but the output voltage will still remain in regulation. This is
V IN(MIN) =
V OUT
D MAX
generally more preferable to skipping cycles and causing
larger ripple at the output, which is typically seen in fixed
frequency switching regulators.
For applications that require relatively low on-time, proper
caution has to be taken when choosing the power MOSFET.
If the gate of the MOSFET is not able to fully turn on due
to insufficient on-time, there could be significant heat dis-
sipation and efficiency loss as a result of larger R DS(ON) .
This may even cause early failure of the power MOSFET.
The minimum off-time is the smallest duration of time
that the TG pin can be turned low and then immediately
turned back high. This minimum off-time includes the
time to turn on the BG (bottom gate) and turn it back off,
plus the dead-time delays from TG off to BG on and from
BG off to TG on. The minimum off-time that the LTC3876
can achieve is 90ns.
The effective minimum off-time of the switching regulator,
or the shortest period of time that the SW node can stay
At the onset of drop-out, there is a region of V IN of about
500mV that generates two discrete off-times, one being
the minimum off time and the other being an off-time that
is about 40ns to 60ns longer than the minimum off-time.
This secondary off-time is due to the extra delay in trip-
ping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output
in regulation. There may be higher SW node jitter, apparent
especially when synchronized to an external clock, but the
output voltage ripple remains relatively small.
Fault Conditions: Current Limiting and Overvoltage
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3876, the maximum sense voltage is controlled
by the voltage on the V RNG pin. With valley current mode
control, the maximum sense voltage and the sense re-
sistance determine the maximum allowed inductor valley
current. The corresponding output current limit is:
+ ? Δ I L
low,canbedifferentfromthisminimumoff-time.Themain
factor impacting the effective minimum off-time is the top
and bottom power MOSFETs’ electrical characteristics,
I LIMIT =
V SENSE(MAX)
R SENSE
1
2
such as Qg and turn-on/off delays. These characteristics
can either extend or shorten the SW nodes’ effective
minimum off-time. Large size (high Qg) power MOSFETs
generally tend to increase the effective minimum off-time
due to longer gate charging and discharging times. On
The current limit value should be checked to ensure that
I LIMIT(MIN) > I OUT(MAX) . The current limit value should
be greater than the inductor current required to produce
maximum output power at the worst-case efficiency.
3876f
32
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