参数资料
型号: LTC3876EFE#PBF
厂商: Linear Technology
文件页数: 4/48页
文件大小: 0K
描述: IC CTLR DC/DC DDR DUAL 38-TSSOP
产品培训模块: LTC3876 Dual DC/DC Controller
标准包装: 50
应用: 控制器,DDR,DDR2,DDR3
输入电压: 4.5 V ~ 38 V
输出数: 2
输出电压: 可调
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 38-TFSOP (0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 38-TSSOP 裸露焊盘
包装: 管件
LTC3876
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T A = 25°C. V IN = 15V unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Start-Up and Shutdown
V RUN(TH)
RUN Pin On Threshold
V RUN Rising
l
1.15
1.2
1.25
V
V RUN(HYS)
I RUN(OFF)
I RUN(HYS)
RUN Pin On Hysteresis
RUN Pin Pull-Up Current When Off
RUN Pin Pull-Up Current Hysteresis
V RUN Falling from V RUN(TH)
RUN = SGND
I RUN(HYS) = I RUN(ON) – I RUN(OFF)
100
2.5
10
mV
μA
μA
V UVLO(INTVCC)
INTV CC Undervoltage Lockout
INTV CC Falling
INTV CC Rising
l
l
3.3
3.7
4.2
4.5
V
V
I TRACK/SS
Soft-Start Pull-Up Current
0V < TRACK/SS < 0.6V
1
μA
Frequency and Clock Synchronization
f CLKOUT
Clock Output Frequency
R T = 205k
200
kHz
(Steady-State Switching Frequency)
R T = 80.6k
450
500
550
kHz
R T = 18.2k
2000
kHz
φ VTT
φ CLKOUT
V CLKOUT(H)
V CLKOUT(L)
V PLLIN(H)
V PLLIN(L)
R MODE/PLLIN
VTT Channel 2 Phase
(Relative to Channel 1)
CLKOUT Phase
(Relative to Channel 1)
Clock Output Voltage High
Clock Output Voltage Low
Clock Input Voltage High
Clock Input Voltage Low
MODE/PLLIN Input DC Resistance
V PHASMD = SGND
V PHASMD = Floating
V PHASMD = INTV CC
V PHASMD = SGND
V PHASMD = Floating
V PHASMD = INTV CC
Pulling to INTV CC
Pulling to SGND
f MODE/PLLIN >100kHz
f MODE/PLLIN >100kHz
0
2
180
180
240
60
90
120
600
V INTVCC
–0.5
Deg
Deg
Deg
Deg
Deg
Deg
V
V
V
V
Gate Drivers
R TG(UP)1,2
R TG(DOWN)1,2
R BG(UP)1
R BG(UP)2
R BG(DOWN)1,2
TG Driver Pull-Up On-Resistance
TG Driver Pull-Down On-Resistance
BG Driver 1 Pull-Up On-Resistance
BG Driver 2 Pull-Up On-Resistance
BG Driver Pull-Down On-Resistance
TG High
TG Low
BG1 High
BG2 High
BG Low
2.5
1.2
2.5
1.6
0.8
Ω
Ω
Ω
Ω
Ω
T D(TG/BG)1,2
T D(BG/TG)1,2
Top Gate Off to Bottom Gate On Delay Time (Note 6)
Bottom Gate Off to Top Gate On Delay Time (Note 6)
20
15
ns
ns
VTT Reference
VTTR(I VTTR )
VTTR Load Regulation
(VTTR(I VTTR ) is Measured Through an
Internal Kelvin Connection to the VTTR Pin
–50mA < I VTTR < 50mA; T A = –40°C to 125°C
1.5 < VDDQ < 2.5
1.0 < VDDQ < 1.5
l
l
0.4940
0.4930
0.5060
0.5070
V/V
V/V
and is Specified as the Ratio (VTTR(I VTTR )/
VDDQ)
Internal V CC Regulator
V DRVCC1
? V DRVCC1
V EXTVCC(TH)
Internal Regulated DRV CC1 Voltage
DRV CC1 Load Regulation
EXTV CC Switchover Voltage
6V < V IN < 38V
I CC = 0mA to 100mA
EXTV CC Rising
5.0
4.4
5.3
–1.5
4.6
5.6
–3
4.8
V
%
V
V EXTVCC(HYS)
EXTV CC Switchover Hysteresis
200
mV
? V DRVCC2
EXTV CC to DRV CC2 Voltage Drop
V EXTVCC = 5V, I DRVCC2 = 100mA
200
mV
3876f
4
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