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参数资料
| 型号： | LTC4099EUDC#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/36页 |
| 文件大小： | 0K |
| 描述： | IC USB PWR MANAGER/CHRGR 20-QFN |
| 标准包装： | 91 |
| 系列： | PowerPath™ |
| 功能： | 电源管理 |
| 电池化学： | 锂离子（Li-Ion）、锂聚合物（Li-Pol） |
| 电源电压： | 4.35 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（3x4） |
| 包装： | 管件 |
| 产品目录页面： | 1341 (CN2011-ZH PDF) |
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LTC4099
PIN FUNCTIONS
IRQ (Pin 8): Open-Drain Interrupt Output. The IRQ pin
can be used to generate an interrupt due to a multitude
of maskable status change events within the LTC4099.
See Table 1.
GND (Pin 9, Exposed Pad Pin 21): Ground. The Exposed
Pad and pin must be soldered to the PCB to provide a low
electrical and thermal impedance connection to ground.
IDGATE (Pin 10): Ideal Diode Amplifier Output. This pin
controls the gate of an external P-channel MOSFET tran-
sistor used to supplement the internal ideal diode. The
source of the P-channel MOSFET should be connected to
V OUT and the drain should be connected to BAT.
BAT (Pin 11): Single-Cell Li-Ion Battery Pin. Depending
on available power and load, a Li-Ion battery on BAT will
either deliver system power to V OUT through the ideal
diode or be charged from the battery charger.
V OUT (Pin 12): Output Voltage of the Switching PowerPath
Controller and Input Voltage of the Battery Charger. The
majority of the portable product should be powered from
V OUT . The LTC4099 will partition the available power be-
tween the external load on V OUT and the internal battery
charger. Priority is given to the external load and any extra
power is used to charge the battery. An ideal diode from
BAT to V OUT ensures that V OUT is powered even if the load
exceeds the allotted power from V BUS or if the V BUS power
source is removed. V OUT should be bypassed with a low
impedance multilayer ceramic capacitor.
V BUS (Pin 13): Input Voltage for the Switching PowerPath
Controller. V BUS will usually be connected to the USB port
of a computer or a DC output wall adapter. V BUS should
be bypassed with a low impedance multilayer ceramic
capacitor.
SW (Pin 14): Switching Regulator Power Transmission
Pin. The SW pin delivers power from V BUS to V OUT via the
step-down switching regulator. An inductor should be con-
nected from SW to V OUT . See the Applications Information
section for a discussion of inductance value.
DV CC (Pin 15): Logic Reference for the I 2 C Serial Port. A
0.01μF bypass capacitor is required.
SCL (Pin 16): Clock Input for the I 2 C Serial Port. The I 2 C
input levels are scaled with respect to DV CC .
SDA (Pin 17): Data Input/Output for the I 2 C Serial Port.
The I 2 C input levels are scaled with respect to DV CC .
ACPR (Pin 18): Auxiliary Power Source Present Output
(Active Low). ACPR indicates that the output of an external
high voltage step-down switching regulator connected to
WALL is suitable for use by the LTC4099. ACPR may be
connected to the gate of an external P-channel MOSFET
transistor whose source is connected to V OUT and whose
drain is connected to WALL. ACPR has a high level of V OUT
and a low level of GND.
CLPROG (Pin 19): USB Current Limit Program and Monitor
Pin. A 1% resistor from CLPROG to ground determines
the upper limit of the current drawn from the V BUS pin.
A precise fraction of the input current, h CLPROG , is sent
to the CLPROG pin when the high side switch is on. The
switching regulator delivers power until the CLPROG pin
reaches 1.18V. Therefore, the current drawn from V BUS
will be limited to an amount given by h CLPROG and
R CLPROG . There are a multitude of ratios for h CLPROG
available by I 2 C control, two of which correspond to the
100mA and 500mA USB specifications (see Table 2). A
multilayer ceramic averaging capacitor is also required at
CLPROG for filtering.
OVSENS (Pin 20): Overvoltage Protection Sense Input.
OVSENS should be connected through a 6.2k resistor to
the input power connector and the drain of an external
N-channel MOSFET pass transistor. When the voltage
on this pin exceeds V OVCUTOFF , the OVGATE pin will be
pulled to GND to disable the pass transistor and protect
the LTC4099 from potentially damaging high voltage.
4099fd
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