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参数资料
| 型号： | LTC4099EUDC#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 27/36页 |
| 文件大小： | 0K |
| 描述： | IC USB PWR MANAGER/CHRGR 20-QFN |
| 标准包装： | 91 |
| 系列： | PowerPath™ |
| 功能： | 电源管理 |
| 电池化学： | 锂离子（Li-Ion）、锂聚合物（Li-Pol） |
| 电源电压： | 4.35 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（3x4） |
| 包装： | 管件 |
| 产品目录页面： | 1341 (CN2011-ZH PDF) |
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LTC4099
APPLICATIONS INFORMATION
nonlinear characteristic of capacitance versus voltage.
The actual in-circuit capacitance of a ceramic capacitor
should be measured with a small AC signal and DC bias,
as is expected in-circuit. Many vendors specify the ca-
pacitance versus voltage with a 1V RMS AC test signal and,
as a result, overstate the capacitance that the capacitor
will present in the application. Using similar operating
conditions as the application, the user must measure
or request from the vendor the actual capacitance to
determine if the selected capacitor meets the minimum
capacitance that the application requires.
Overprogramming the Battery Charger
The USB high power specification allows for up to 2.5W
to be drawn from the USB port. The LTC4099’s switching
regulator regulates the voltage at V OUT to a level just
above the voltage at BAT while limiting power to less
than the amount programmed at CLPROG. The charger
should be programmed, with the PROG pin, to deliver
the maximum safe charging current without regard to
the USB specifications. If there is insufficient current
available to charge the battery at the programmed rate,
the charger will reduce charge current until the system
load on V OUT is satisfied and the V BUS current limit is
satisfied. Programming the charger for more current
than is available will not cause the average input cur-
rent limit to be violated. It will merely allow the battery
charger to make use of all available power to charge the
battery as quickly as possible, and with minimal power
dissipation within the charger.
Overvoltage Protection
It is possible to protect both V BUS and WALL from
overvoltage damage with several additional components
as shown in Figure 5. Schottky diodes D1 and D2 pass
the larger of V1 and V2 to R1 and OVSENS. If either
V1 or V2 exceeds 6V plus the Schottky forward voltage,
OVGATE will be pulled to GND and both the WALL and
USB inputs will be protected. Each input is protected up
to the drain-source breakdown, BV DSS , of M1 and M2.
In an overvoltage condition, the OVSENS pin will be
clamped at 6V. The external 6.2k resistor must be
sized appropriately to dissipate the resultant power.
For example, a 1/8W 6.2k resistor can have at most
√1/8W × 6.2k = 28V applied across its terminals.
With the 6V at OVSENS, the maximum overvoltage
magnitude that this resistor can withstand is 34V. A
1/4W 6.2k resistor raises this value to 45V. OVSENS’s
absolute maximum current rating of 10mA imposes an
upper limit of 68V protection.
Table 10. Recommended NMOS FETs for the Overvoltage
Protection Circuit
NMOS FET BV DSS R ON PACKAGE
FDN3725 30V 50mΩ SOT-23
Si2302ADS 20V 70mΩ SOT-23
NTLJS4114 30V 40mΩ 2mm × 2mm DFN
IRLML2502 20V 35mΩ SOT-23
The charge pump output on OVGATE has limited output
drive capability. Care must be taken to avoid leakage on
this pin as it may adversely affect operation.
V1
M1
WALL
OVGATE
LTC4099
V2
D2
D1
M2
C1
V BUS
GND
R1
OVSENS
4099 F05
Figure 5. Dual Overvoltage Protection
4099fd
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