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参数资料
| 型号： | LTC4099EUDC#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 30/36页 |
| 文件大小： | 0K |
| 描述： | IC USB PWR MANAGER/CHRGR 20-QFN |
| 标准包装： | 91 |
| 系列： | PowerPath™ |
| 功能： | 电源管理 |
| 电池化学： | 锂离子（Li-Ion）、锂聚合物（Li-Pol） |
| 电源电压： | 4.35 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（3x4） |
| 包装： | 管件 |
| 产品目录页面： | 1341 (CN2011-ZH PDF) |
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LTC4099
APPLICATIONS INFORMATION
USB Inrush Limiting
Voltage overshoot on V BUS may sometimes be observed
when connecting the LTC4099 to a lab power supply. This
overshoot is caused by long leads from the power supply
to V BUS . Twisting the wires together from the supply to
V BUS can greatly reduce the parasitic inductance of these
long leads, and keep the voltage at V BUS to safe levels. USB
cables are generally manufactured with the power leads in
close proximity, and thus fairly low parasitic inductance.
Board Layout Considerations
The Exposed Pad on the backside of the LTC4099 package
must be securely soldered to the PC board ground. This
is the primary ground pin in the package, and it serves
as the return path for both the control circuitry and the
synchronous rectifier.
Furthermore, due to its high frequency switching
circuitry, it is imperative that the input capacitor, inductor,
and output capacitor be as close to the LTC4099 as pos-
sible, and that there be an unbroken ground plane under
the LTC4099 and all of its external high frequency compo-
nents. High frequency currents, such as the input current
on the LTC4099, tend to find their way on the ground plane
along a mirror path directly beneath the incident path on
the top of the board. If there are slits or cuts in the ground
plane due to other traces on that layer, the current will be
forced to go around the slits. If high frequency currents are
not allowed to flow back through their natural least-area
path, excessive voltage will build up and radiated emis-
sions will occur (see Figure 9). There should be a group of
vias directly under the grounded backside leading directly
down to an internal ground plane. To minimize parasitic
inductance, the ground plane should be as close as pos-
sible to the top plane of the PC board (layer 2).
The IDGATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an additional offset
to the ideal diode of approximately 10mV. To minimize
leakage, the trace can be guarded on the PC board by
surrounding it with V OUT connected metal, which should
generally be less than 1V higher than IDGATE.
Battery Charger Stability Considerations
The LTC4099’s battery charger contains both a constant-
voltage and a constant-current control loop. The con-
stant-voltage loop is stable without any compensation
when a battery is connected with low impedance leads.
Excessive lead length, however, may add enough series
inductance to require a bypass capacitor of at least 1μF
from BAT to GND.
4099 F09
Figure 9. Higher Frequency Ground Currents Follow
Their Incident Path. Slices in the Ground Plane Cause
High Voltage and Increased Emissions
4099fd
0
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