参数资料
型号: LTC4110EUHF#PBF
厂商: Linear Technology
文件页数: 43/52页
文件大小: 0K
描述: IC BATTERY BACKUP MANAGER 38-QFN
标准包装: 52
功能: 备份管理
电池化学: 铅酸,锂离子,锂聚合物,镍镉,镍氢,超级电容器
电源电压: 4.5 V ~ 19 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 38-WFQFN 裸露焊盘
供应商设备封装: 38-QFN(5x7)
包装: 管件
产品目录页面: 1341 (CN2011-ZH PDF)
LTC4110
APPLICATIONS INFORMATION
The V DS ratings of the MOSFETs need to be higher than
these values.
The MOSFET current ratings for the primary side must be
higher than I PRI , which is I PRI(CHG) or I PRI(CAL) for charge
and Calibration mode respectively. See Equations 1 and 2.
MOSFET current ratings for the secondary side must be
higher than I PRI /N. Since both MOSFETs must perform
both roles, the minimum current rating of the MOSFETs
should be greater than the higher of these values.
MOSFET power dissipation is a function of the RMS cur-
rent ?owing through the MOSFET.
Charge Mode:
I PRI ( FETCHG ) =
I CHG V BAT ? ( V BAT + N ? V DCIN )
?
E V DCIN
The MOSFET should be speci?ed for fast or PWM switching.
The MOSFET that meets all the above speci?cations but
has the lowest Q G and/or Q GD is often the best choice.
PowerPath MOSFET SELECTION
Important parameters for the selection of PowerPath
MOSFETS are the maximum drain-source voltage V DS(MAX) ,
threshold voltage V GS(VT) , on-resistance R DS(ON) and
Q GATE .
The maximum allowable drain-source voltage, V DS(MAX) ,
must be high enough to withstand the maximum drain-
source voltage seen in the application.
The gates of these MOSFETs are driven by the INID (Input
Ideal Diode) and BATID (Battery Ideal Diode) pins. The
gate turn-on voltage, V GS , is set by the smaller of the
PowerPath supply voltage or the internal clamping volt-
age V GON . For the MOSFET driven from the INID pin its
I SEC ( FETCHG ) = I CHG ?
Calibration Mode:
I PRI ( FETCAL ) = I CAL ?
I SEC ( FETCAL ) =
V BAT + N ? V DCIN
N ? V DCIN
V BAT + N ? V DCIN
N ? V DCIN
PowerPath supply voltage is the higher of the DCIN pin
or DCOUT pin voltage. For the MOSFETs driven from the
BATID pin, their PowerPath supply voltage is the higher
of the DCOUT pin or BAT pin voltage. Logic-level V GS(VT)
MOSFET is commonly used, but if a low supply voltage
limits the gate voltage a sub-logic-level threshold MOSFET
should be considered.
As a general rule, select a MOSFET with a low enough
R DS(ON) to obtain the desired V DS while operating at full
I CAL ? E ?
V BAT ? ( V BAT + N ? V DCIN )
V DCI N
current load and an achievable V GS . The MOSFET normally
operates in the linear region and acts like a voltage con-
trolled resistor. If the MOSFET is grossly undersized then it
Where I PRI(FETCHG) is the same FET as I SEC(FETCAL) and
I PRI(FETCAL) is the same FET as I SEC(FETCHG) .
Using the equation below, plug in the higher current from
above into I FET to ?nd each FET’s power dissipation for
the given mode.
P FET = I FET2 ? R DS(ON)
The R DS(ON) value of the MOSFET depends on V GS . Conser-
vatively you can use the R DS(ON) value with a V GS rating of
4.5V. If you are using a dual-MOSFET package, determine
whether charge mode or calibration mode results is the
highest overall power dissipation and use that as the rating
for the dual MOSFET.
can enter the saturation region and a large V DS may result.
However, the drain-source diode of the MOSFET, if forward
biased will limit V DS . A large V DS combined with the load
current could result in excessively high MOSFET power
dissipation. Keep in mind that the LTC4110 will regulate
the forward voltage drop across the MOSFETs at 20mV
(V FR ) if R DS(ON) is low enough. The required R DS(ON) can
be calculated by dividing 0.02V by the load current in amps.
Achieving forward regulation will minimize power loss and
heat dissipation, but it is not a necessity. If a forward volt-
age drop of more than 20mV is acceptable then a smaller
MOSFET can be used, but must be sized compatible with the
higher power dissipation. Care should be taken to ensure
4110fb
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