- 您现在的位置：买卖IC网 > PDF目录224123 > M25P40-VMN6TG/X (NUMONYX) 512K X 8 SPI BUS SERIAL EEPROM, PDSO8 PDF资料下载
参数资料
| 型号： | M25P40-VMN6TG/X |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 512K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件页数： | 10/57页 |
| 文件大小： | 1160K |
| 代理商： | M25P40-VMN6TG/X |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
Instructions
M25P40
18/57
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select (S) must be driven High after the last bit of the instruction sequence has been
shifted in.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Power-
down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when
the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
相关PDF资料 |
PDF描述 |
|---|---|
| M25P40VMF6 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P40VMF6G | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P40VMF6P | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P40VMF6T | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P40VMF6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M25P40VMN6TP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
| M25P40-VMN6TP | 功能描述:闪存 SERIAL SECTOR ERASE FLASH 4MEG RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| M25P40-VMN6TP/X | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface |
| M25P40-VMN6TP_NUD | 制造商:Micron Technology Inc 功能描述: |
| M25P40-VMN6TPB | 功能描述:IC FLASH 4MBIT 75MHZ 8SOIC RoHS:是 类别:集成电路 (IC) >> 存储器 系列:Forté™ 标准包装:2,000 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 异步 存储容量:256K (32K x 8) 速度:15ns 接口:并联 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:28-TSSOP（0.465"，11.8mm 宽） 供应商设备封装:28-TSOP 包装:带卷 (TR) 其它名称:71V256SA15PZGI8 |
发布紧急采购，3分钟左右您将得到回复。