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参数资料
| 型号： | M295V200T-55M1R |
| 厂商： | 意法半导体 |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 连接器附件 |
| 文件页数： | 5/33页 |
| 文件大小： | 224K |
| 代理商： | M295V200T-55M1R |
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CommandInterface
Instructions,made up of commands written in cy-
cles,can be givento theProgram/EraseController
through a Command Interface (C.I.). For added
dataprotection,program or erase executionstarts
after4 or6cycles.Thefirst,second,fourthandfifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrectcommand or any improper command se-
quencewill reset the deviceto ReadArray mode.
Instructions
Seven instructions are defined to perform Read
Array,AutoSelect(to readtheElectronicSignature
or BlockProtectionStatus),Program,BlockErase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations.The StatusRegisterData Polling, Tog-
gle, Error bits and the RB output may be read at
anytime, duringprogrammingor erase,to monitor
the progress of the operation.
Instructionsare composedof upto six cycles. The
first two cycles input a Coded sequence to the
CommandInterfacewhich iscommontoall instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
outputtheaddresseddata,ElectronicSignatureor
Block Protection Status for Read operations. In
orderto giveadditionaldataprotection,the instruc-
tionsfor Programand Blockor Chip Erase require
furthercommandinputs.ForaPrograminstruction,
the fourth command cycle inputs the addressand
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Codedsequence before the Erase confirm
commandon thesixth cycle.Erasure of a memory
blockmaybesuspended,inorderto readdatafrom
anotherblock or to programdata in anotherblock,
and then resumed.
When power is first applied or if V
CC
falls below
V
LKO
, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table1.
Address Inputs (A0-A16)
. The addressinputsfor
thememoryarrayarelatchedduringa writeopera-
tion on the falling edge of Chip Enable E or Write
EnableW. In Word-wide organisationthe address
lines are A0-A16, in Byte-wide organisation
DQ15A–1acts as an additionalLSB address line.
When A9 is raised to V
ID
, either a Read Electronic
Signature Manufacturer or Device Code, Block
Protection Status or a Write Block Protection or
Block Unprotection is enabled depending on the
combinationof levelson A0, A1,A6, A12 andA15.
Data Input/Outputs (DQ0-DQ7).
These In-
puts/Outputsare used in theByte-wide and Word-
wide organisations. The input is data to be
programmed in the memory array or a command
to be written to the C.I. Both are latched on the
rising edge of Chip Enable E or Write Enable W.
The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
registerData Polling bitDQ7, the ToggleBits DQ6
and DQ2, the Error bit DQ5or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsaredisabledandwhenRPisat aLowlevel.
Data Input/Outputs (DQ8-DQ14 and DQ15A–1).
These Inputs/Outputsare additionallyused in the
Word-wideorganisation.WhenBYTEis HighDQ8-
DQ14 and DQ15A–1 act as the MSB of the Data
Input or Output, functioningas describedfor DQ0-
DQ7 above, and DQ8-DQ15 are ’don’t care’ for
command inputs or statusoutputs. When BYTEis
Low,DQ8-DQ14arehighimpedance,DQ15A–1is
theAddressA–1 input.
Chip Enable (E).
The Chip Enable input activates
the memory control logic, input buffers, decoders
andsenseamplifiers.EHighdeselectsthememory
andreducesthepowerconsumptiontothestandby
level. E can also be used to control writing to the
command register and to the memory array, while
Wremainsat alowlevel.TheChipEnablemustbe
forced to V
ID
duringthe Block Unprotectionopera-
tion.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
ID
level during
BlockProtectionand Unprotectionoperations.
WriteEnable(W).
Thisinputcontrolswritingto the
CommandRegisterand Addressand Datalatches.
Byte/Word Organization Select (BYTE).
The
BYTEinputselectsthe outputconfigurationfor the
device: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTEis Low,the Byte-widemode is
selectedand the data is read and programmedon
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is se-
lected and the data is read and programmed on
DQ0-DQ15.
5/33
M29F200T, M29F200B
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| M295V200T-55M1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:2 Mbit 256Kb x8 or 128Kb x16, Boot Block Single Supply Flash Memory |
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