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参数资料
| 型号： | M295V400T-55N6R |
| 厂商： | 意法半导体 |
| 英文描述： | 4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory |
| 中文描述： | 4兆位512KB的x8或256Kb的x16插槽，启动座单电源闪存 |
| 文件页数： | 9/34页 |
| 文件大小： | 231K |
| 代理商： | M295V400T-55N6R |
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INSTRUCTIONSAND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structionsrequirefrom 1 to6 cycles,the firstor first
three of which are always writeoperations used to
initiate the instruction. They are followed by either
furtherwritecycles to confirmthe first command or
executethe commandimmediately. Commandse-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security.
Instructions are initialised by two initial Coded cy-
cleswhichunlock theCommand Interface. In addi-
tion, for Erase, instruction confirmation is again
preceded by the two Coded cycles.
StatusRegister Bits
P/E.C.statusis indicatedduringexecution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mandexecutionwillautomatically outputthesefive
StatusRegisterbits.The P/E.C.automatically sets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
Data Polling Bit (DQ7).
When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
DuringErase operation, it outputsa ’0’.After com-
pletionof theoperation, DQ7will output thebit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after thefourth W pulse for programming or
after the sixth W pulse for erase. It must be per-
formed at theaddress being programmed or at an
address within the block being erased. If all the
blocksselectedfor erasureare protected, DQ7will
be setto ’0’for about100
μ
s,and thenreturnto the
previous addressed memory data value. See Fig-
ure 11 for the Data Polling flowchart and Figure 10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
onablockbeingerasedand thedatavalueonother
blocks. During Program operation in Erase Sus-
pendMode, DQ7 will have the samebehaviour as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6).
When Programming or Erasing
operations are in progress, successiveattempts to
readDQ6willoutput complementarydata.DQ6will
toggle following toggling of either G, or E when G
is low. The operation is completed when two suc-
cessivereadsyieldthe sameoutput data.The next
readwilloutputthe bitlastprogrammed ora’1’after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100
μ
s and then
returnbacktoRead. DQ6 will be setto ’1’ifa Read
operationisattemptedonan EraseSuspend block.
When erase is suspended DQ6 will toggle during
programming operationsin a blockdifferent to the
block in EraseSuspend. Either E or Gtoggling will
cause DQ6 to toggle. See Figure 12 for Toggle Bit
flowchart and Figure 13 for Toggle Bit waveforms.
Hex Code
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
Table 7. Commands
9/34
M29F400T, M29F400B
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相关代理商/技术参数 |
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|---|---|
| M295V400T-55N6TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory |
| M295V400T-70M1R | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory |
| M295V400T-70M1TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory |
| M295V400T-70M3R | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory |
| M295V400T-70M3TR | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:4 Mbit 512Kb x8 or 256Kb x16, Boot Block Single Supply Flash Memory |
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