参数资料
型号: M6MGB166S2BWG
厂商: Mitsubishi Electric Corporation
英文描述: CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-CSP
中文描述: 3.3的CMOS只快闪记忆体
文件页数: 13/30页
文件大小: 253K
代理商: M6MGB166S2BWG
Nov 1999 , Rev.2.3
MITSUBISHI LSIs
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
M6MGB/T166S2BWG
13
3.3V
GND
F-V
CC
Vcc POWER UP / DOWN TIMING
V
IH
V
IL
F-RP#
Read /Write Inhibit
t
VCS
V
IH
V
IL
F-CE#
V
IH
V
IL
F-WE#
t
PS
t
PS
Read /Write Inhibit
Read /Write Inhibit
TEST CONDITIONS
FOR AC CHARACTERISTICS
Input voltage : V
IL
= 0V, V
IH
= 3.0V
Input rise and fall times :
5ns
Reference voltage
at timing measurement : 1.5V
Output load : 1TTL gate +
CL(30pF)
or
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
OUTPUT VALID
HIGH-Z
t
DF(OE)
t
RC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
ADDRESSES
F-CE#
F-OE#
F-WE#
DATA
ADDRESS VALID
t
OH
t
OLZ
t
a (CE)
t
OEH
t
CLZ
t
a (AD)
t
a (OE)
HIGH-Z
DUT
3.3k
W
1N914
1.3V
C
L
=30pF
V
IH
V
IL
F-RP#
t
PS
t
DF(CE)
t
PHZ
t
RE
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
OUTPUT VALID
HIGH-Z
t
DF(OE)
t
RC
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
ADDRESSES
F-CE#
F-OE#
F-WE#
DATA
ADDRESS VALID
t
OH
t
OLZ
t
a (CE)
t
RE
t
CLZ
t
a (AD)
t
a (OE)
HIGH-Z
V
IH
V
IL
F-RP#
t
PS
t
DF(CE)
t
PHZ
Valid
FFH or 71H
In the case of application F-CE# is Low fixed, it is allowed to define a timming specification of tRE
from rising edge of F-WE# to falling edge of F-OE#, and valid data is read after spec of tRE+ta(CE).
(This is only for FFH,71H program and read)
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