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参数资料
| 型号： | MAX11008EVC16 |
| 厂商： | Maxim Integrated |
| 文件页数： | 42/67页 |
| 文件大小： | 0K |
| 描述： | EVAL KIT MAX11008 |
| 标准包装： | 1 |
| 系列： | * |
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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Interpolated Data = DATA 1 + ? ? x ( DATA 2 ? DATA 1 )
4) The resulting LUT pointer value is bound-limited to
ensure it fits within the corresponding LUT. Negative
pointer values are limited to zero, and pointer values
that extend beyond the range of the LUT are limited
to the last entry.
5) The final LUT pointer value is calculated by shifting
SOT to the left by 5 bits and then adding it to the
current LUT pointer value. If no linear interpolation
(INT = 00) is to be performed, the resulting LUT
pointer value is equal to the absolute EEPROM
address from which the LUT data is retrieved. If lin-
ear interpolation is to be performed (INT = 01, 10, or
11), the two LUT addresses that are closest to the
resulting LUT pointer value and their corresponding
data values are entered into the following equation
to calculate the interpolated data value that is used
in the V GATE_ calculation:
? PTR ? ADD 1 ?
? ADD 2 ? ADD 1 ?
where PTR is the calculated LUT pointer value with
fractional bits, ADD1 and ADD2 are the two LUT
addresses closest to the value of PTR, and DATA1 and
DATA2 are the LUT data values stored at ADD1 and
ADD2.
LUT Pointer Example 1 (No Interpolation)
POFF = 001000 (offset of +8).
INT = 00 (no interpolation/LUT pointer does not have
any fractional bits).
PSIZE = 00 (5-bit LUT pointer not including any frac-
tional bits).
TSIZE = 001 (LUT has 32 data locations).
SOT = 010 (LUT starts at EEPROM address 40 hex).
Table 5b. Fractional Bits Added to LUT
Pointer for Linear Interpolation
NUMBER OF FRACTIONAL BITS ADDED TO
INT
LUT POINTER
Table 5. Temperature/APC LUT
Configuration Register
00
01
10
0
1 ≥ 1:2 interpolation
2 ≥ 1:4 interpolation
DATA
BITS
BIT
NAME
RESET
STATE
FUNCTION
11
3 ≥ 1:8 interpolation
D[15:10]
POFF
000000
POFF bits.
Table 5c. Selectable LUT Sizes
D[9:8]
INT
00
Interpolation degree select bits.
See Table 5b.
TSIZE
000
Unused
LUT SIZE
D[7:6]
D[5:3]
D[2:0]
PSIZE
TSIZE
SOT
00
000
000
LUT pointer size bit. See Table
5a.
LUT size bit. See Table 5c.
Start of table address bits. See
Table 5d.
001
010
011
100
101
Table size of 32 data locations
Table size of 64 data locations
Table size of 96 data locations
Table size of 128 data locations
Table size of 160 data locations
Table 5a. LUT Pointer Sizes and Offset
Ranges
110
111
Table size of 192 data locations
Unused
PSIZE
00
LUT POINTER SIZE
5-bit pointer (access up
to 32 data locations)
POFF OFFSET RANGE*
-32 to +31
Table 5d. Selectable LUT Starting
Addresses
SOT STARTING ADDRESS IN EEPROM (HEX)
01
10
11
6-bit pointer (access up
to 64 data locations)
7-bit pointer (access up
to 128 data locations)
8-bit pointer (access up
to 256 data locations)
-32 to +31
-64 to +62 (in steps of 2)
-128 to +124 (in steps of 4)
000
001
010
011
100
101
Unused
Unused
0x40
0x60
0x80
0xA0
*POFF is either a negative or positive number. When POFF is
negative its value is represented in two’s complement format.
110
111
0xC0
0xE0
42
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