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参数资料
| 型号： | MAX11008EVC16 |
| 厂商： | Maxim Integrated |
| 文件页数： | 60/67页 |
| 文件大小： | 0K |
| 描述： | EVAL KIT MAX11008 |
| 标准包装： | 1 |
| 系列： | * |
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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Software Clear Register (SCLR) (Write Only)
Write to the Software Clear register to clear the internal
registers with a single write command (see Table 25).
Bits D[15:7] are don’t-care bits.
FULLRST and ARMRST operate in conjunction with
each other to allow a full hardware reset of the device.
If ARMRST has been set to 1 by a previous write com-
mand, setting FULLRST to 1 initiates a full reset of the
MAX11008. ARMRST can only be set to 1 when the
FULLRST is set to 0 in the same data word. This pro-
vides protection from accidental resets since two write
commands are needed to initiate a full reset. To per-
form a full reset, first write a data word with FULLRST
set to 0 and ARMRST set to 1. Then write another data
word with FULLRST set to 1 and ARMRST set to 0.
Set the ALMSCLR bit to 1 to clear all alarm threshold
registers and their respective flags in the Flag register.
Set the AVGCLR bit to 1 to clear the average and hys-
teresis memory for all lookup operations. Setting the
AVGCLR bit reacquires the average and performs a
new LUT operation.
Table 17. DAC Input Registers
Set FIFOCLR to 1 to clear the FIFO. This function is
instantaneous and does not affect BUSY.
Set DAC_RST to 1 to clear the contents of the DAC
Input and Output registers. This function is instanta-
neous and does not affect BUSY.
Flag Register (FLAG) (Read Only)
The Flag register indicates if the MAX11008 is currently
in the middle of an internal calculation, if a full reset has
been performed, and the status of the FIFO. The Flag
register also indicates the source of an alarm when an
alarm threshold is exceeded (see Table 26). Bits
D[15:12] are don’t-care bits.
ALUBUSY is set to 1 when the MAX11008 is performing
an internal calculation (see the Busy Output section)
and returns to 0 when the calculation is complete.
RESTART is set to 1 if a full reset or watchdog initiated
reset was performed (see the Software Clear Register
(SCLR) (Write Only) section) and returns to 0 after the
Flag register is read. RESTART is initially set to 0 when
power is first applied (a power-on reset condition).
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
DACIP_[11:0]
RESET STATE
XXXX
NA
Unused bits.
DAC Input register data bits.
FUNCTION
X = Don’t care.
NA = Not applicable.
Table 18. DAC Input and Output Register
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
DAC_[11:0]
RESET STATE
X
NA
FUNCTION
Unused bits.
DAC Input and Output register data bits.
X = Don’t care.
NA = Not applicable.
60
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